Rate-Limited Shared Buffers for Image Processing Throughput
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Solution Overview
Problem
Image processing pipelines are often bottlenecked by memory access speeds, leading to inefficient use of system resources and increased power consumption due to CPU bandwidth consumption when software-based processing is employed, and existing hardware solutions do not effectively manage data retrieval and allocation among multiple processing operations.
Innovation Solution
An image signal processor with a dynamically shared buffer arbitrated by a rate limiter circuit, which allocates data credits and throttles excess allocations to manage data exchange among multiple pixel pipelines, ensuring fair use of system resources and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based image processing is employed on CPU, then image processing can be performed with flexibility, but CPU bandwidth consumption increases and power consumption increases
Solution Approach 1:
The patent replaces software-based image processing on CPU with dedicated hardware image processing circuits. These circuits are specifically designed to perform image processing operations in hardware, eliminating the need for CPU intervention and thereby reducing CPU bandwidth consumption and power usage while maintaining processing flexibility through configurable hardware modules.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the image processing circuits and system memory. This buffer manages data exchange and allocation, allowing multiple processing operations to access memory resources efficiently without direct CPU involvement, thus reducing CPU bandwidth consumption while enabling flexible image processing.
2Productivity
If multiple processing operations are carried out simultaneously in image processor, then processing throughput increases, but memory access speed becomes a bottleneck
Solution Approach 1:
The patent segments the buffer into multiple sections, with each section dedicated to specific processing operations or pipelines. This segmentation allows simultaneous access by multiple processing circuits without contention for the same memory resources, enabling high throughput while avoiding memory access bottlenecks through parallelized data retrieval.
Solution Approach 2:
The patent implements preliminary data retrieval and pre-processing operations that prepare image data in advance for subsequent processing stages. By pre-fetching and organizing data in the buffer before it is needed by processing circuits, the system enables multiple operations to proceed simultaneously without waiting for slow memory access, thus maintaining high throughput.
3Productivity
If buffer is shared among multiple image processing circuits, then resource utilization efficiency increases, but allocation management complexity increases
Solution Approach 1:
The patent implements a self-service buffer allocation mechanism where each image processing circuit is equipped with control logic that automatically manages its own buffer allocation and data retrieval. This decentralized approach allows multiple circuits to share the buffer efficiently without requiring complex centralized arbitration, reducing allocation management complexity while maintaining high resource utilization.
Data Source
AI summary
Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.