Redistributed Chip Package Planarization via Raised Contacts

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Solution Overview

Problem

Conventional Redistributed Chip Packaging (RCP) processes face challenges in encapsulating semiconductor die with microelectronic components having irregular terminals, leading to non-planar surfaces, defects in Redistribution Layers (RDL), and increased electrical shorts due to topological irregularities.

Innovation Solution

A method is introduced to create a planar frontside surface on the molded panel by forming raised contacts over the semiconductor die bond pads before encapsulation, which are then polished along with the microelectronic components' terminals, ensuring a smooth surface for subsequent RDL deposition and reducing material loss and damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional RCP processes encapsulate semiconductor die with microelectronic components having irregular terminals, then packaging versatility is improved, but surface planarity deteriorates leading to non-planar surfaces and topological irregularities

Engineering Contradiction:

Improvepackaging versatilityVSAvoidsurface planarity

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarization layer over the encapsulated semiconductor die and microelectronic components before depositing the redistribution layers. This pre-planarization step ensures that subsequent RDL deposition occurs on a flat surface, eliminating topological irregularities while maintaining the ability to package diverse components with irregular terminals.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If polishing is performed on non-planar surfaces with irregular terminals, then surface smoothness is improved, but material loss and component damage increase

Engineering Contradiction:

Improvesurface smoothnessVSAvoidmaterial loss and component damage

Core Design Contradiction:

Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent introduces a planarization layer as an intermediary material between the irregular terminals and the polishing process. This layer absorbs the mechanical stress and material removal during polishing, protecting the underlying microelectronic components from damage while still achieving a smooth surface for subsequent processing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The planarization layer is applied before polishing to create a uniform surface topology. This preliminary protective layer ensures that polishing removes material uniformly from the planarization layer itself rather than from the sensitive component terminals, significantly reducing material loss and damage.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If Redistribution Layers are deposited on non-planar surfaces, then electrical interconnection is achieved, but defect density increases leading to electrical shorts

Engineering Contradiction:

Improveelectrical interconnectionVSAvoiddefect density

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent performs planarization by depositing a planarization layer and polishing it to flatness before depositing the redistribution layers. This ensures that the RDLs are formed on a perfectly planar surface, eliminating voids, pinholes, and other defects that would otherwise occur when depositing on non-planar surfaces, thereby reducing electrical shorts and improving reliability.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes surface defects in RDL layers, enhances electrical insulation, and increases product yield by providing a controlled environment for polishing and interconnect formation, facilitating the packaging of semiconductor die with diverse microelectronic components.

Implementation Method 1

The molded panel is polished to create a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed

Methodology Applied

Scientific EffectMechanical polishing: Abrasion

Data Source

PatentUS8822268B1Redistributed chip packages containing multiple components and methods for the fabrication thereof

Publication Date: 2014.09.02 NXP USA INC

AI summary

Embodiments of a method for fabricating Redistributed Chip Packages are provided, as are embodiments of Redistributed Chip Packages. In one embodiment, the method includes the steps/processes of embedding a first semiconductor die and a microelectronic component in a molded panel having a frontside, the first semiconductor die comprising a plurality of bond pads over which a plurality of raised contacts has been formed. The frontside of the molded panel is polished to impart the molded panel with a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed. Finally, at least one redistribution layer is build or produced over the substantially planar surface to electrically interconnect the first semiconductor die and the microelectronic component.