Redistribution Layer Electroplating for Uniform Metal Line Heights
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Solution Overview
Problem
Existing electroplating processes for forming redistribution layers (RDLs) in semiconductor packages result in uneven metal line heights due to loading effects, leading to varying via lengths and potential mechanical and electrical reliability issues.
Innovation Solution
A modified electroplating process using a specialized electroplating apparatus and adjusted chemical concentrations and current profiles to control the height difference between wide and narrow metal lines, employing a two-step plating current application and optimized additive ratios to ensure uniform deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electroplating process is used to form metal lines, then copper deposition is achieved, but uneven heights in metal lines of different widths occur due to loading effects
Solution Approach 1:
The patent applies parameter changes by modifying the electroplating process parameters, specifically using a two-step plating current approach (initial low current followed by higher current) and optimizing chemical concentrations (copper ion concentration less than sulfuric acid concentration, and less than hydrochloric acid concentration). These parameter adjustments compensate for loading effects and achieve uniform metal line heights across different widths, resolving the contradiction between manufacturing precision and reliability.
2Manufacturing precision
If conventional electroplating is used, then copper deposition is achieved, but varying via lengths result from uneven metal line heights
Solution Approach 1:
The patent employs preliminary action by first forming uniform metal lines through optimized electroplating before subsequently forming vias. The two-step plating process (initial low current to establish uniform base height, then higher current for completion) ensures that metal lines are uniformly leveled before via formation, preventing varying via lengths and ensuring consistent contact reliability.
3Productivity
If standard electroplating process is used, then RDL formation is achieved, but height differences between wide and narrow metal lines exceed acceptable limits
Solution Approach 1:
The patent implements periodic action through a two-step plating current process. The first step uses a lower current density to uniformly deposit copper on all line widths, then the second step increases current density to complete the plating. This periodic variation in plating conditions maintains both productivity and height uniformity, keeping height differences between wide and narrow lines below 0.5 μm.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified process effectively reduces the height disparity between wide and narrow metal lines to less than 0.5 μm, enhancing mechanical and electrical reliability of RDLs by minimizing defects and contact resistance.
Implementation Method 1
The plating solution includes copper ions, sulfuric acid, and hydrochloric acid. The electroplating process forms a redistribution layer on the semiconductor structure through electrochemical deposition.
Implementation Method 2
performing an electrochemical reaction on the plating solution to form a redistribution layer on the semiconductor structure
Data Source
AI summary
A semiconductor device includes an interconnect structure over a substrate and a redistribution layer over the interconnect structure. The redistribution layer includes a first via, a first metal line disposed on the first via, a second via, and a second metal line disposed on the second via. A width of the first metal line is greater than a width of the second metal line. A thickness of the first metal line is equal to a thickness of the second metal line. Each of the first and second metal lines includes a top portion having a conductive material of a first grain size and a bottom portion having the conductive material of a second grain size. The first grain size is greater than the second grain size.