RDL Interposer 3D Semiconductor Package Wire Length Reduction
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges such as increased thickness, limited fine pitch pad support, low-resistance/inductance, and high costs due to expensive substrates, particularly in flip-chip packages, where bump pitch development lags behind die shrinking and pin count increases, and TSV-based solutions are expensive and complex.
Innovation Solution
A non-TSV based, three-dimensional (3D) wire-bonding semiconductor package incorporating a redistribution layer (RDL) interposer that reduces wire length and provides RF shielding between SoC and DRAM die, using a silicon or resin interposer to transmit signals and alleviate overhang issues between stacked chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flip-chip packaging is used to increase I/O pin count, then interconnection density is improved, but bump pitch development lags behind die shrinking and substrate cost increases
Solution Approach 1:
The patent divides the substrate into multiple separate carrier substrates, each carrying a subset of chips. This segmentation allows each carrier substrate to have a simpler, more manageable bump pitch configuration while achieving high overall I/O pin count through the assembly of multiple carriers.
Solution Approach 2:
The patent transitions from a two-dimensional substrate layout to a three-dimensional stacked configuration with carrier substrates positioned at different vertical levels. This dimensional change enables increased I/O capacity by utilizing vertical space rather than being constrained by planar substrate area.
2Reliability
If TSV-based technologies are used to conquer technology gap, then interconnection capability is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the TSV (Through-Silicon Via) component from the manufacturing process. Instead of using TSV-based technologies, the invention employs wire bonding and bump interconnections on carrier substrates, thereby maintaining interconnection capability while removing the associated manufacturing complexity and cost.
Solution Approach 2:
The patent replaces expensive, complex TSV-based interconnection structures with simpler, more cost-effective wire bonding and surface-mount bump technologies. These alternative methods achieve sufficient interconnection reliability without requiring costly through-silicon via fabrication processes.
3Speed
If wire length is reduced in 3D stacked package, then signal performance is improved, but RF shielding requirements increase
Solution Approach 1:
The patent introduces ground planes and shielding structures as intermediary elements between signal-carrying traces on different carrier substrates. These intermediaries provide RF shielding to protect against electromagnetic interference while allowing the short wire length configuration to maintain fast signal transmission.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.