Semiconductor Package RDL Structure for Stacked Chip Connectivity
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Solution Overview
Problem
As the number of stacked semiconductor chips in multi-chip packages increases, it becomes increasingly difficult to effectively connect signal lines, leading to challenges in electrical connectivity and efficient voltage supply.
Innovation Solution
The implementation of a redistribution layer (RDL) structure with redistribution lines and wires that provide conductive paths to connect semiconductor chips independently, ensuring stable voltage supply and reducing resistance and inductance by electrically connecting multiple redistribution lines and wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor chips is increased to achieve higher integration, then the integration capacity is improved, but the difficulty of connecting signal lines increases
Solution Approach 1:
The patent transitions from planar signal line connections to three-dimensional stacked chip connections using vertical vias and redistribution layers. This dimensional change enables signal routing between multiple chip layers, allowing higher integration while managing connection complexity through structured vertical interconnects rather than sprawling planar traces.
Solution Approach 2:
The signal connection system is segmented into distinct functional layers: individual chip signal lines, redistribution layers on intermediate substrates, and vertical via connections. This segmentation allows each layer to be optimized independently, reducing the overall complexity of connecting multiple stacked chips while maintaining high integration capacity.
2Reliability
If more redistribution lines are added to connect stacked chips independently, then electrical connectivity is improved, but the resistance and inductance increase causing power loss
Solution Approach 1:
Multiple redistribution lines carrying similar signals or power are merged into shared conductive paths where appropriate. By consolidating redundant or parallel signal routes, the patent reduces the total number of individual connections, thereby lowering cumulative resistance and inductance while maintaining electrical connectivity across stacked chips.
Solution Approach 2:
The patent employs three-dimensional routing with vertical vias and layered redistribution structures to create shorter, more direct signal paths between stacked chips. This dimensional approach reduces the length of conductive paths compared to planar routing, thereby minimizing resistance and inductance effects while ensuring reliable electrical connectivity.
3Stability of the object's composition
If redistribution lines extend over the chip surface to provide conductive paths, then voltage supply stability is improved, but the area occupied by the RDL structure increases
Solution Approach 1:
The redistribution layer structure is segmented into multiple functional zones: power distribution regions, signal routing regions, and via connection regions. This segmentation allows voltage supply paths to be concentrated in specific areas rather than uniformly distributed, maintaining voltage stability while minimizing the overall area occupied by the RDL structure on the chip surface.
Solution Approach 2:
The patent applies different design characteristics to different regions of the RDL structure. High-current power distribution paths are localized to specific areas with optimized trace widths and spacing, while signal routing uses different patterns. This local optimization ensures voltage supply stability where needed while reducing the total area occupied by the RDL structure.
Data Source
AI summary
A semiconductor package offers improved product reliability by supplying a power voltage and a ground voltage to a semiconductor chip in a secured manner using a redistribution layer (RDL) structure. The semiconductor package includes a first semiconductor chip disposed on a substrate, a second semiconductor chip disposed on the first semiconductor chip, a plurality of redistribution lines disposed on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip, and a redistribution wire disposed on the first semiconductor chip and electrically connecting one of the redistribution lines to another.