RDL Over Top Package for PoP Semiconductor Interconnect
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Solution Overview
Problem
The existing methods for forming redistribution layers (RDLs) in package-on-package (PoP) semiconductor devices are slow and costly, leading to higher fabrication costs and increased package thickness due to the need for both front and backside interconnects, which complicates electrical interconnection between stacked semiconductor packages.
Innovation Solution
The formation of a build-up interconnect structure with a redistribution layer (RDL) over the top semiconductor package, which simplifies manufacturing by integrating RDL components into the top package, reducing the need for separate front and backside interconnects and minimizing thermal stress, while allowing for flexible routing design and increased integration compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RDLs are formed over both front and back sides of the bottom package for electrical interconnection, then electrical connectivity is achieved, but manufacturing becomes slow and costly with higher fabrication costs
Solution Approach 1:
The patent extracts the RDL formation process from the bottom package and relocates it to the top package. Specifically, the RDL is formed over the front side of the top package instead of forming RDLs over both sides of the bottom package, thereby simplifying the manufacturing process while maintaining electrical connectivity between stacked packages
Solution Approach 2:
Instead of the conventional approach of forming interconnects on the bottom package, the patent inverts the approach by forming the RDL on the top package. This reversal of the standard manufacturing sequence reduces the number of manufacturing steps and lowers fabrication costs
2Reliability
If RDLs are formed over both front and back sides of the bottom package, then electrical interconnection is achieved, but fabrication costs increase
Solution Approach 1:
The patent removes the complex dual-side RDL formation process from the bottom package and extracts only the necessary interconnection function, implementing it instead through a single RDL layer on the top package, thereby reducing fabrication complexity and cost
Solution Approach 2:
The patent combines the interconnection function that would require separate RDL formations on both sides of the bottom package into a single integrated RDL structure on the top package, simplifying the manufacturing process and reducing fabrication costs
3Reliability
If separate front and backside interconnects are used, then electrical connection is achieved, but package thickness increases
Solution Approach 1:
The patent extracts the backside interconnect structure from the design, retaining only the essential front-side RDL on the top package for electrical connection, thereby reducing the overall package thickness while maintaining functional electrical connectivity
Solution Approach 2:
Instead of adding thickness through separate front and backside interconnects on the bottom package, the patent inverts the approach by using a single RDL on the top package, thereby achieving electrical connection with reduced package thickness
Data Source
AI summary
A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.