RDL and TSV Integration via Isolation Trench Etching
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling integrated circuits due to limitations in the fabrication of re-distribution layers (RDL) and through-silicon vias (TSV), where deeper vias result in larger TSV sizes and RDL integration is often not simultaneous, leading to increased costs and larger die sizes.
Innovation Solution
The method involves etching an isolation trench to form a low resistance Si-pillar as a TSV electrical conduction path and a RDL, filling it with poly-silicon and oxide, and bonding a cap wafer to a semiconductor device to create a smaller TSV size and integrate RDL and TSV simultaneously, utilizing wafer level chip scale package (WLCSP) technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If deeper vias are used to achieve higher integration density, then the I/O connection capability is improved, but the TSV size increases leading to larger die size
Solution Approach 1:
The patent segments the via structure into two parts: a first via extending from the first surface to a intermediate depth, and a second via extending from the first surface to the second surface. This segmentation allows the via system to achieve deep penetration for I/O connection while maintaining a compact footprint by distributing the via functions across multiple smaller via structures rather than requiring a single large via.
2Manufacturing precision
If RDL and TSV are fabricated separately to ensure process quality, then the manufacturing precision is maintained, but the fabrication complexity and cost increase
Solution Approach 1:
The patent merges the RDL and TSV fabrication processes into a single integrated process flow. The isolation trench is formed to define both the RDL region and the TSV region simultaneously. The same etching, deposition, and planarization steps that form the RDL also define and prepare the TSV structures. This merging maintains manufacturing precision because both structures are formed using the same controlled processes, while reducing fabrication complexity by eliminating separate process sequences.
3Ease of manufacture
If traditional separate fabrication processes are used for RDL and TSV, then process control is easier, but the production efficiency decreases
Solution Approach 1:
The patent implements continuous useful action by forming the RDL and TSV structures in an uninterrupted sequence within a single process flow. The isolation trench formation, material deposition, and planarization steps continuously build both the RDL and TSV structures without interrupting the manufacturing sequence. This eliminates idle time between separate RDL and TSV fabrication processes, thereby improving production efficiency while maintaining process control through consistent manufacturing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a smaller TSV size for the same depth and simultaneous fabrication of RDL and TSV, reducing fabrication costs and achieving a smaller die size, while providing an input/output connection point through the TSV and RDL.
Implementation Method 1
filling it with poly-silicon and oxide
Implementation Method 2
bonding a cap wafer to a semiconductor device
Data Source
AI summary
A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package is disclosed. The method comprises preparing a wafer for bonding to a semiconductor package. The wafer comprises a low resistance substrate containing a RDL and a TSV for making an input/output (I/O) connection point of the semiconductor package available at another location. The RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation trench. The TSV is bounded by the isolation trench and the RDL. Preparing the wafer for bonding may comprise preparing the isolation trench that bounds the conduction path for the RDL through the low resistance substrate and bounds a vertical conduction path in a pillar for the TSV in the low resistance substrate, filling the isolation trench with isolation trench material, and preparing a wafer bonding surface.