Read Data Rearrangement Using Multiphase Clock Phase Detection
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Solution Overview
Problem
Semiconductor memories experience out-of-sequence read data due to clocking operations that are out-of-phase, leading to synchronization issues and delayed access times, which are challenging to resolve without causing timing inaccuracies.
Innovation Solution
Implementing a data register with a multiplexer control circuit that rearranges read data based on phase relationships between internal and external clocks, ensuring synchronized data output by correcting out-of-phase clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If internal clocks are used to provide multiphase clocks for timing data operations, then data transfer timing is improved, but read data may be output out of sequence due to out-of-phase clocking
Solution Approach 1:
The patent applies preliminary action by detecting the phase relationship between internal and external clocks before data output operations occur. The system determines whether internal clocks are in-phase or out-of-phase with external clocks in advance, and pre-configures the data output circuit accordingly to prevent out-of-sequence data output. This advance detection and preparation ensures that data is always output in the correct sequence regardless of clock phase relationships.
2Reliability
If clock swapping is performed to resolve out-of-sequence read data, then data sequence accuracy is improved, but synchronization between external and internal clocks becomes challenging resulting in delayed access times
Solution Approach 1:
The patent applies dynamics by making the data output circuit configurable and adaptive based on detected clock phase relationships. Rather than performing static clock swapping operations that cause delays, the system dynamically adjusts the data output circuit's behavior to match the actual phase relationship between internal and external clocks. This dynamic adaptation eliminates the need for time-consuming clock swapping while maintaining data sequence accuracy.
3Stability of the object's composition
If synchronous clock swapping is implemented to preserve clock synchronization, then phase alignment is improved, but timing inaccuracies and access time delays occur
Solution Approach 1:
The patent introduces an intermediary detection mechanism that monitors the phase relationship between internal and external clocks without requiring direct intervention or swapping operations. This intermediary detection system provides real-time information about clock phase alignment, allowing the data output circuit to adjust its behavior accordingly. This approach maintains phase alignment accuracy without the timing inaccuracies and delays associated with synchronous clock swapping operations.
Data Source
AI summary
Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.