Dynamic Read Strobe Trimming for Low-Power LP-DDR Timing

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Solution Overview

Problem

Low power dual data rate (LP-DDR) memory systems face challenges in maintaining invariant delays due to process-voltage-temperature (PVT) variations, which affect data access timing and power consumption, especially in mobile applications where extreme temperature changes are common, and existing solutions like DLLs consume excessive power.

Innovation Solution

A system and method for dynamic trimming that generates a reference clock signal, uses a counter to produce clock pulses at a slower frequency, and employs a phase length detector with a trimmer chain to detect and transform average pulse lengths into phase delays, allowing for adaptive delay adjustments to maintain invariant read strobe timing under varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a delay lock loop (DLL) is used to obtain invariant delays in the read strobe, then delay stability is improved, but power consumption increases significantly

Engineering Contradiction:
Improvedelay stabilityVSAvoidpower consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic trimming by periodically measuring the actual delay through phase length detection and adjusting the trimmer chain accordingly. This dynamic adaptation allows the system to maintain delay stability without the continuous high power consumption of a DLL, as trimming occurs only when needed rather than continuously locking the phase.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs self-adjustment by using its own operational characteristics (phase length of clock pulses) to determine the required trim value. The phase length detector measures the actual delay and feeds this information back to adjust the trimmer chain, enabling the system to self-correct delay variations without external intervention or high-power continuous control.

Inventive Principle:
Principle #25Self-service

2Use of energy by moving object

If a static trimmer value is used to delay the read strobe, then power consumption is reduced, but adaptability to PVT variations deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidadaptability to PVT variations
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent transitions from static to dynamic trimming by periodically measuring the phase length of clock pulses and adjusting the trimmer chain based on actual conditions. This allows the system to adapt to PVT variations while maintaining lower power consumption compared to continuous DLL operation, as trimming is performed on-demand rather than continuously.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by using the phase length detector to measure actual delay characteristics and using this information to adjust the trimmer chain. This closed-loop approach enables the system to adapt to changing conditions while consuming significantly less power than open-loop continuous control methods like DLLs.

Inventive Principle:
Principle #23Feedback

3Reliability

If the operating frequency is reduced to account for PVT variations, then reliability is improved, but productivity decreases

Engineering Contradiction:
Improveoperational reliabilityVSAvoiddata access speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the delay parameter dynamically by adjusting the trimmer chain based on measured phase length. This allows the system to maintain optimal timing characteristics across different operating conditions and frequencies, enabling reliable operation at higher frequencies than would be possible with fixed static trimmers designed for conservative frequency margins.

Inventive Principle:
Principle #35Parameter changes

4Adaptability or versatility

If dynamic trimming is implemented to track operating conditions, then adaptability to PVT variations is improved, but device complexity increases

Engineering Contradiction:
Improveadaptability to PVT variationsVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the delay control function into distinct components: a phase length detector that measures actual delay, a trimmer chain that provides adjustable delay, and control logic that adjusts the trimmer based on measurements. This segmentation allows each component to be optimized independently and simplifies the overall design compared to implementing a full DLL.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs partial trimming actions only when needed rather than continuous control. By periodically measuring phase length and adjusting trimmer values only when deviations are detected, the system achieves adaptability with reduced circuit complexity compared to continuous control mechanisms like DLLs that require extensive phase detection and continuous adjustment circuitry.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7966509B2System and method for performing low power dynamic trimming
Publication Date: 2011.06.21 NVIDIA CORP
  • US7966509B2 patent drawing
  • US7966509B2 patent drawing
  • US7966509B2 patent drawing

AI summary

A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled to the clock and generates a plurality of clock pulses based on pulses of the reference clock signal. The plurality of clock pulses is generated at a slower frequency from the first frequency for low power operation. A phase length detector is coupled to the counter and comprises a trimmer chain for detecting an average length of at least one of the generated plurality of clock pulses. A transformation module is coupled to the phase length detector for transforming the average length to a phase delay of the signal.