Ready-Signal-Gated Data Pipeline Circuit for Lower Power
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Solution Overview
Problem
The tradeoff between maximum system clock frequency and data wire length in integrated circuits leads to increased propagation delay and power consumption due to the use of latches in data pipeline circuits, limiting data transfer efficiency.
Innovation Solution
A data pipeline circuit design that includes an upstream and downstream interface circuit with a logic circuit comprising first and second data storage circuits and a status circuit, where data storage in the second data storage circuit is conditioned on the readiness of the downstream circuit to receive data, reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data pipeline circuits with latches are used to break long propagation paths, then the clock frequency can be increased, but power consumption increases
Solution Approach 1:
The patent applies dynamic control to the data pipeline circuit by using the ready signal to conditionally enable or disable latch operations. The system dynamically adjusts its operation based on whether the downstream circuit is ready to receive data, thereby reducing unnecessary power consumption while maintaining the ability to operate at high clock frequencies when needed.
Solution Approach 2:
The patent changes the operational parameters of the data pipeline circuit by introducing conditional data storage based on the ready signal state. When the downstream circuit is not ready, the circuit transitions to a low-power state by preventing unnecessary latch operations, thus reducing power consumption while maintaining the capability to operate at high frequencies when the downstream circuit is ready.
2Reliability
If data is stored in the second data storage circuit continuously, then data availability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by storing data in the second data storage circuit only when necessary - specifically when the downstream circuit is not ready to receive data. This conditional approach ensures data availability is maintained when needed while avoiding unnecessary power consumption from continuous or excessive data storage operations.
Solution Approach 2:
The patent uses feedback from the ready signal to control data storage operations in the second data storage circuit. The ready signal provides information about the downstream circuit's readiness state, and this feedback is used to conditionally enable or disable data storage, thereby balancing data availability with power consumption efficiency.
3Productivity
If the system operates at higher clock frequencies, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by operating the data pipeline circuit at high clock frequencies only during periods when the downstream circuit is ready to receive data. During periods when the downstream circuit is not ready, the circuit transitions to a low-power state. This periodic high-frequency operation maintains high data transfer speed when needed while reducing average power consumption.
Data Source
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AI summary
A data pipeline circuit (300) includes an upstream interface circuit (304) that receives sequential data and a downstream interface circuit (306) that transfers the sequential data to a downstream circuit (310(D)). A ready signal (READY) indicates the downstream circuit (310(D)) is ready to receive the sequential data. The data pipeline circuit (300) includes a first data latch (302(1)), a second data latch (302(2)) and a first status latch (326). The first data latch (302(1)) receives the sequential data. The first status latch (326) generates an available signal (324) that is asserted to indicate the second data latch (302(2)) is available to receive the sequential data. The second data latch (302(2)) receives the sequential data in response on the available signal (324) being asserted and the ready signal (READY) indicating the downstream circuit (310(D)) is not ready to receive the sequential data on the data output (OUTDATA). Limiting conditions in which the sequential data is stored in the second data latch (302(2)) significantly reduces power consumption of the data pipeline circuit (300).