Receiver Bias Circuit Pre-Charging for Fast USB2 Repeater Startup
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Solution Overview
Problem
The shrinking of SoC node size, especially at 7 nm and below, leads to design challenges for USB2.0 interfaces due to the requirement of 3.3V I/O voltage, which is difficult to support, resulting in high manufacturing costs and power inefficiencies, and existing repeaters struggle to achieve fast startup times while maintaining power savings.
Innovation Solution
The design of a USB2/eUSB2 repeater with a receiver and transmitter that utilize bias circuits and driver circuits to enable fast startup, including pre-charging of critical nodes and a pull-down path to optimize bias currents and reduce startup time to less than 4 ns, while maintaining power efficiency by disabling the signal path during idle mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bias circuits are continuously enabled to achieve fast startup, then startup speed is improved, but power consumption increases
Solution Approach 1:
The bias circuits are pre-enabled before the receiver and transmitter paths are activated, so that when the signal path is enabled, the bias circuits are already in their operational state, achieving fast startup without continuous power consumption during idle periods
Solution Approach 2:
The bias circuits transition from a static always-on state to a dynamic state where they are enabled only when needed, allowing the system to adapt power consumption based on operational requirements while maintaining fast startup capability
2Use of energy by moving object
If signal path is disabled during idle mode to save power, then power efficiency is improved, but startup time increases
Solution Approach 1:
The bias circuits are activated in advance during idle mode preparation, so when the signal path needs to be enabled, the bias circuits are already ready, eliminating startup delay while maintaining power savings during extended idle periods
Solution Approach 2:
The system prepares the bias circuits in advance during idle mode, creating a cushion of readiness that ensures fast startup can occur immediately when signal transmission is required, without incurring continuous power consumption
3Adaptability or versatility
If 3.3V I/O voltage is used in 7 nm SoC nodes, then compatibility with USB2.0 is maintained, but manufacturing cost and power consumption increase
Solution Approach 1:
The system dynamically adjusts voltage parameters, operating at 3.3V when USB2.0 compatibility is required and potentially switching to lower voltage modes when full compatibility is not needed, reducing manufacturing complexity and power consumption while maintaining adaptability
Data Source
AI summary
Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.