Receiver Circuit Level Shifting for High-Voltage CMOS Inputs
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Solution Overview
Problem
The challenge is to develop a semiconductor receiver circuit that can efficiently handle high-voltage signals using a low-voltage process, as existing CMOS processes for high-voltage signals are expensive and require separate transistors for high and low voltage levels, increasing manufacturing costs and complexity.
Innovation Solution
The proposed solution involves a receiver circuit with restriction circuits, PMOS and NMOS transistors, and compensation resistors that adjust reference voltages to manage high and low voltage levels, allowing the circuit to operate under a low-voltage process while supporting high-voltage signals, and includes hysteresis setting parts for precise signal handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CMOS process is used to fabricate high-voltage tolerant elements, then the chip can receive various levels of signals, but the manufacturing cost increases
Solution Approach 1:
The patent changes the voltage parameters of standard transistors through circuit-level design rather than process-level changes. By using voltage restriction circuits and compensation resistors, the circuit can handle high-voltage signals (up to 3.3V or higher) while being fabricated with low-voltage CMOS processes (1.8V or lower), eliminating the need for expensive dual-voltage CMOS processes
Solution Approach 2:
The patent introduces intermediary circuits (voltage restriction circuits, compensation resistors, and level conversion circuits) between the high-voltage input signal and the low-voltage transistor gates. These intermediaries convert or limit the voltage levels, allowing standard low-voltage transistors to safely process high-voltage signals without requiring high-voltage tolerant process fabrication
2Adaptability or versatility
If separate transistors are used for high-voltage and low-voltage levels, then signal handling capability is improved, but device complexity increases
Solution Approach 1:
The patent makes standard low-voltage transistors multi-functional by adding protection and level conversion circuits. The same transistor can handle both normal low-voltage logic operations and high-voltage signal reception, eliminating the need for separate high-voltage and low-voltage transistor sets. The voltage restriction circuits enable a single transistor to serve multiple voltage domains
Solution Approach 2:
The patent combines high-voltage signal reception functionality with standard low-voltage logic circuits. By integrating voltage restriction circuits, compensation resistors, and level conversion stages into the existing logic circuit architecture, the design merges high-voltage tolerance with low-voltage operation in a unified circuit structure rather than using separate dedicated circuits
3Adaptability or versatility
If voltage levels are converted to logical levels, then compatibility with low-voltage process is achieved, but signal processing accuracy may be affected
Solution Approach 1:
The patent employs feedback mechanisms through compensation resistors and hysteresis circuits that monitor the voltage levels and adjust the switching thresholds accordingly. The compensation resistors provide feedback to maintain accurate voltage division ratios, ensuring that high-voltage signals are converted to logical levels with preserved signal integrity and noise margins
Solution Approach 2:
The patent applies beforehand cushioning by introducing compensation resistors and voltage restriction circuits that pre-establish proper voltage levels and protection before signals reach the sensitive transistor gates. These circuits cushion against voltage excursions and noise, ensuring accurate signal conversion to logical levels while maintaining signal integrity throughout the conversion process
Data Source
AI summary
Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.