Receiver Clock Frequency Limiting During Data Interruptions
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Solution Overview
Problem
In computer systems, PLL-based clock recovery circuits experience a rapid increase in frequency when the incoming data stream is interrupted, leading to potential loss of logical state due to the inability to align transitions in noise, causing errors and setup/hold time failures.
Innovation Solution
A receiver circuit with a measurement circuit that monitors the clock frequency and generates an indication signal when it exceeds a threshold, allowing the clock generator circuit to adjust the frequency, preventing it from exceeding operational limits and initiating an orderly shutdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock generator circuit continues to operate without data input, then the clock frequency increases rapidly, but this causes loss of logical state and processing errors
Solution Approach 1:
The measurement circuit proactively monitors clock frequency and detects runaway conditions before they cause logical state loss. The system takes preliminary action by generating an indication signal when frequency exceeds threshold, enabling corrective action before damage occurs
Solution Approach 2:
The system implements feedback control by continuously measuring clock frequency and comparing it against a threshold. When the frequency exceeds the threshold, the measurement circuit sends an indication signal back to the clock generator circuit to reduce frequency, thereby maintaining reliability while allowing speed optimization
2Loss of time
If the measurement circuit monitors clock frequency continuously, then frequency runaway is detected rapidly, but this increases device complexity
Solution Approach 1:
Rather than implementing complex system-wide monitoring, the solution places a dedicated measurement circuit locally at the clock generator output. This localized approach enables rapid frequency detection with minimal added complexity, as the monitoring function is confined to a specific component rather than distributed throughout the entire system
Data Source
AI summary
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.