Receiver Equalizer Balancing for ISI Timing Recovery Convergence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Achieving time synchronicity between a transmitter and a receiver under inter-symbol interference conditions is challenging, as timing recovery mechanisms may fail to converge correctly or lock into a wrong steady state, and simultaneous convergence of equalizers and timing recovery mechanisms is often impossible due to inter-dependencies.
Innovation Solution
A two-phase timing recovery mechanism is employed, where a first type decision-directed timing recovery mechanism is used to decrease the receiver's local clock frequency to match the transmitter's symbol clock frequency, followed by a second type mechanism capable of increasing and decreasing frequencies to achieve phase-lock, while a configurable analog equalizer and Feed Forward/Decision Feedback Equalizers are used to adapt to inter-symbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an equalizer and timing recovery mechanism are used simultaneously to correct inter-symbol interference, then signal quality is improved, but convergence into correct steady state operation becomes impossible or non-deterministic due to inter-dependencies
Solution Approach 1:
The patent segments the equalization process into two distinct phases: a training phase where the equalizer converges using known training symbols, and a decision-directed phase where the timing recovery mechanism operates. This segmentation eliminates the inter-dependency conflict by establishing a clear sequence where the equalizer first converges independently, then the timing recovery mechanism converges using the already-equalized signal, ensuring deterministic convergence without simultaneous interaction conflicts
Solution Approach 2:
The patent applies preliminary action by having the equalizer converge during the training phase before the timing recovery mechanism begins operation. The equalizer uses known training symbols to establish correct coefficients and steady state operation in advance, creating a stable foundation that allows the timing recovery mechanism to subsequently converge reliably without the complications of simultaneous convergence attempts
2Stability of the object's composition
If a moderate high-pass frequency response is used in the analog equalizer, then stability is improved, but compensation for low-pass frequency response of the physical link becomes insufficient
Solution Approach 1:
The patent implements dynamics by making the analog equalizer's high-pass frequency response adjustable rather than fixed. During the training phase, the high-pass response is set to a moderate level for stability. During the decision-directed phase, the high-pass response is dynamically increased to a higher level to provide aggressive compensation for the low-pass characteristics of the physical link, thereby achieving both stability during convergence and effective compensation during operation
Solution Approach 2:
The patent applies parameter changes by modifying the high-pass frequency response parameter of the analog equalizer based on the operational phase. The system transitions from a moderate high-pass response parameter setting during training to a more aggressive high-pass response parameter setting during decision-directed operation, allowing the system to optimize both stability and compensation effectiveness at different stages
Data Source
AI summary
A configurable analog equalizer is set to a first high-pass frequency response that is intentionally too moderate to compensate for a low-pass frequency response of a physical link coupling a transmitter and a receiver. A Feed Forward Equalizer (FFE) is activated at the receiver; the FFE includes a set of coefficients having a minimum configuration of a cursor coefficient and a first pre-cursor coefficient. A Decision Feedback Equalizer (DFE) is activated at the receiver; the DFE includes a set of coefficients having a minimum configuration of a first post-cursor coefficient. The configurable analog equalizer is then set to a high-pass frequency response that is more intense than the first high-pass frequency response, until the first post-cursor coefficient of the DFE substantially equals an absolute value of a quotient obtained by dividing the first pre-cursor coefficient of the FFE by the cursor coefficient of the FFE.