Receiver Module III-V FET Voltage Dissipation
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Solution Overview
Problem
Existing receiver modules in optocouplers lack efficient voltage dissipation and self-locking mechanisms, leading to slow voltage decay and potential short circuits, especially in dark conditions.
Innovation Solution
A receiver module featuring an optically operated voltage source with a III-V semiconductor-based FET transistor structure, where a normally on field effect transistor short-circuits the voltage source contacts if the voltage falls below a threshold, and a Schottky diode is integrated to manage the voltage and prevent short circuits, utilizing III-V semiconductor layers and a non-Si substrate for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a voltage source is used in the receiver module, then voltage generation is achieved, but voltage dissipation is slow in dark conditions
Solution Approach 1:
The patent extracts the voltage dissipation function from the voltage source itself by introducing a separate field-effect transistor switch. This transistor is specifically designed to provide a discharge path for the voltage source when light is absent, separating the voltage generation and dissipation functions into distinct components that can operate independently and efficiently.
Solution Approach 2:
The patent implements a feedback mechanism where the field-effect transistor switch responds to the light detection status of the voltage source. When the voltage source detects darkness (absence of light), it automatically activates the transistor to dissipate voltage, and when light is present, the transistor remains inactive. This closed-loop feedback ensures rapid voltage dissipation only when needed.
2Productivity
If the FET transistor structure is made small, then manufacturing efficiency improves, but voltage rise characteristics may be affected
Solution Approach 1:
The patent optimizes the FET transistor dimensions by adjusting key parameters such as gate width and channel length to achieve the desired balance between small size and fast voltage rise. Specifically, the gate width is set to 0.5 mm to 2 mm and channel length to 0.5 mm to 2 mm, which provides sufficient switching speed while maintaining compact dimensions for efficient manufacturing and integration.
3Reliability
If III-V semiconductor layers are used, then optoelectronic performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the voltage source and field-effect transistor switch into a single integrated device structure where both components share common III-V semiconductor layers and are fabricated using the same material system. This integration approach maintains the superior optoelectronic performance of III-V materials while reducing manufacturing complexity by eliminating the need for separate material deposition and processing steps for different components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly accelerates voltage dissipation in dark conditions, prevents short circuits, and allows for the creation of small, efficient FET transistors with improved voltage rise characteristics when light is applied, enhancing the overall performance and cost-effectiveness of the receiver module.
Implementation Method 1
A voltage generated by shining light onto the top of the first stack is present between the two connecting contacts
Implementation Method 2
The FET transistor structure includes a control terminal, i.e., a gate terminal, and a drain terminal and a source terminal. The FET transistor structure is designed as a self-conducting field-effect transistor.
Data Source
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Figure 3
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AI summary
Receiver module (EM) comprising an optically operated voltage source (SP), wherein the voltage source (SP) comprises a first stack (SP1) with a top (OSP1) and a bottom (USP1) and is based on stacked III-V semiconductor layers on a top (OS1) of a non-Si substrate (NSSUB), and has a second electrical connection contact (K2) on the top (OSP1) of the first stack (SP1) and a first electrical connection contact (K1) on a bottom (US1) of the non-Si substrate (NSSUB), wherein a voltage generated by irradiation of light (L) onto the top (OSP1) of the first stack (SP1) is applied between the two connection contacts (K1, K2), and comprising a second stack (ST2) with a MOS transistor structure (MOS1) comprising a III-V semiconductor layer, having a control terminal (G1), a drain terminal (DR1), and a source terminal (S1).wherein the MOS transistor structure (MOS1) is designed as a self-conducting field-effect transistor and the control terminal (G1) is connected to one of the two terminal contacts (K1, K2) and the drain terminal (DR1) to the other of the two terminal contacts (K1, K2), wherein the field-effect transistor short-circuits the two terminal contacts (K1, K2) if the generated voltage falls below a threshold value.