Receiver PLL Frequency Estimation for Fast Clockless Data Sync
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Solution Overview
Problem
Existing high-speed serial interface clocking solutions, particularly embedded clock types, face challenges in synchronization and frequency alignment, requiring additional clock signals and complex synchronization processes, which increase costs and complexity.
Innovation Solution
A method using a phase locked loop (PLL) to sample and estimate the frequency of an incoming signal, setting the PLL to match the estimated frequency, and continuously adjusting for zero phase error to reduce settling time, allowing for asynchronous data reception without a separate clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded clock solutions are used to achieve higher data rates, then productivity is improved, but device complexity increases due to the need for clock and data recovery (CDR)
Solution Approach 1:
The patent extracts the clock signal from the data stream by using a phase-locked loop to lock onto the transitions in the embedded data signal. This allows the receiver to recover the clock information inherently present in the data without requiring separate clock transmission or complex CDR circuits, thereby reducing device complexity while maintaining high data rates
Solution Approach 2:
The data stream itself serves as the clock source by embedding clock information within the data transitions. The receiver uses the data signal's own transitions to synchronize its sampling clock, eliminating the need for external clock signals or complex synchronization mechanisms, thus simplifying the overall system while enabling high-speed operation
2Device complexity
If type 3 plesiochronous clocking is used to reduce connections and simplify hardware, then device complexity is reduced, but reliability decreases due to frequency mismatch issues
Solution Approach 1:
The patent employs a dynamic phase-locked loop that continuously adjusts its phase and frequency to lock onto the incoming data stream transitions. This dynamic adjustment mechanism allows the receiver to adapt to any frequency variations in the embedded clock signal, ensuring reliable synchronization without requiring plesiochronous clock matching or additional reference oscillators, thus maintaining high reliability while simplifying hardware
3Productivity
If frequency estimation and continuous PLL adjustment are implemented to reduce settling time, then productivity is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent implements a frequency estimation mechanism that analyzes the incoming data stream before full synchronization begins. This preliminary frequency determination allows the phase-locked loop to start from a known frequency point rather than searching from scratch, significantly reducing settling time. The estimation circuit uses simple counters and comparators to determine the data rate, adding minimal complexity while enabling fast synchronization
Data Source
AI summary
The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.