Receiver Test Circuit Layout for Low-Parasitic Signal Bumps
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Solution Overview
Problem
Conventional chip designs require large signal bumps at the receiver for high-speed testing, leading to wasted circuit space and significant parasitic capacitance, which hampers the efficiency of electrical testing.
Innovation Solution
A chip and chip test method incorporating a test circuit with a digital-to-analog converter, resistor, and unit gain buffer, or analog-to-digital converter, coupled between the signal receiving unit and signal bump, allowing for effective electrical testing without the need for external probes, thereby reducing the area requirement of signal bumps and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a signal bump with a large area is designed at the receiver to meet DFT requirements for high-speed chip testing, then electrical testing can be performed, but the receiver circuit occupies a large area and parasitic capacitance increases
Solution Approach 1:
A test circuit is introduced as an intermediary component between the signal receiving unit and the signal bump. This test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer, which together enable electrical testing functionality without requiring the signal bump itself to be large. The intermediary test circuit decouples the testing capability from the physical size of the signal bump, allowing small-area signal bumps to still support comprehensive electrical testing through the inserted test circuitry.
2Reliability
If a signal bump with a large area is designed at the receiver to meet DFT requirements, then electrical testing can be performed, but parasitic capacitance becomes significant
Solution Approach 1:
The test circuit serves as an intermediary that enables testing while using small-area signal bumps, thereby reducing the parasitic capacitance that would otherwise be generated by large signal bumps. The test circuit's internal components (digital-to-analog converter, resistor, unit gain buffer) are designed to perform testing functions with minimal parasitic effects compared to enlarging the signal bump itself.
3Reliability
If the receiver circuit occupies a large area, then DFT requirements are met, but circuit space is wasted
Solution Approach 1:
By inserting a test circuit as an intermediary between the signal receiving unit and the signal bump, the invention enables design for testability without requiring the receiver circuit to occupy excessive area. The test circuit consolidates testing functionality in a dedicated module, allowing the rest of the receiver circuit to be compact and efficiently utilize available circuit space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient electrical testing at the signal receiver, reducing the area occupied by signal bumps and improving signal transmission speed while minimizing parasitic capacitance.
Implementation Method 1
The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer
Implementation Method 2
A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer
Implementation Method 3
A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor
Data Source
AI summary
A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.