Recess Channel Floating Gate Memory Cell for Logic Integration
Solution Overview
Problem
The integration of 1.5 T ESF3 memory devices with floating gates is complicated due to higher stack topology, making it difficult to integrate with logic operations, and the short channel effect is significant due to the gate structure.
Innovation Solution
The implementation of recess channel floating gate memory cells with a common source coupling source side injection programming method, which omits control gates, simplifies the structure topology and enhances the coupling ratio and effective channel length, reducing the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate memory cells with control gates are used, then memory functionality is achieved, but structure topology becomes complicated and integration with logic processes becomes difficult
Solution Approach 1:
The patent extracts and removes the control gate component from the floating gate memory cell structure. By taking out the control gate, the structure topology is simplified while the memory functionality is maintained through alternative programming methods (charge trap and hot carrier injection) that do not require the control gate, thus resolving the contradiction between achieving memory functionality and reducing structural complexity
Solution Approach 2:
The patent segments the programming mechanism into two independent methods: charge trap programming and hot carrier injection programming. This segmentation allows the memory cell to function without requiring a control gate, as each programming method can operate independently, thereby simplifying the overall structure while maintaining full memory functionality
2Ease of operation
If conventional gate structures are used, then memory operation is enabled, but short channel effect becomes significant
Solution Approach 1:
The patent introduces recess channels that extend vertically into the substrate, adding a depth dimension to the channel structure. This dimensional change increases the effective channel length without increasing the planar footprint, thereby reducing the short channel effect while maintaining proper memory operation. The recess channel structure allows the channel to extend below the surface level, creating a three-dimensional path for charge carriers
Data Source
AI summary
A memory device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first word line and the second word line may be metal gates of high-k metal gate structures.