Recessed Array Gate Stacks for Simultaneous IC Processing
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Solution Overview
Problem
Integrated circuit fabrication faces challenges in simultaneously processing different types of transistors in various regions of an integrated circuit, requiring complex and time-consuming processes that hinder cost savings and efficiency.
Innovation Solution
A method involving the deposition of a gate electrode layer over semiconductor substrates, etching trenches, and simultaneously recessing metallic materials in one region while patterning gate materials in another, with conformal insulating layers and anisotropic etches to form efficient conductive elements and transistors, allowing for pitch doubling techniques to reduce feature size and increase density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different materials are employed for transistors in array versus peripheral regions, then transistor performance is optimized for each region, but processing complexity increases due to separate masking and construction steps
Solution Approach 1:
A single gate electrode layer is formed that serves dual purposes: it becomes the gate electrode for peripheral transistors and the cap electrode for array transistors. This universal layer is created through blanket deposition over the entire substrate, eliminating the need for separate material deposition processes for different regions and reducing processing complexity while maintaining optimized transistor performance in each region
2Ease of manufacture
If array region is masked off while peripheral devices are constructed, then peripheral transistor fabrication is enabled, but processing time increases
Solution Approach 1:
The fabrication processes for array and peripheral regions are merged into a single simultaneous operation. The gate electrode layer is deposited blanket-wise over the entire substrate, and subsequent etching and formation steps are performed concurrently for both regions using unified process sequences, eliminating the time-consuming sequential masking and separate construction approach
3Manufacturing precision
If pitch doubling techniques are used, then feature size is reduced and density increased, but processing steps become more complex
Solution Approach 1:
The gate electrode layer is deposited and prepared in advance as a blanket layer before region-specific patterning. This preliminary formation of the universal gate layer establishes a common foundation that simplifies subsequent pitch doubling operations, as the layer is already in place and ready for simultaneous processing in both array and peripheral regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of transistors in different regions, reducing processing steps and time, enhancing the density and efficiency of integrated circuit fabrication, particularly in memory devices like DRAMs, while maintaining consistent conductivity and work functions across the array.
Implementation Method 1
An anisotropic etch is conducted on the insulating layer to leave sidewall spacers on the second conductive element and an insulating filler on an upper surface of the recessed first conductive element
Data Source
AI summary
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.