Recessed Channel Structure in FDSOI Transistors
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Solution Overview
Problem
Scaling the thickness of the semiconductor device layer in fully depleted semiconductor on insulator (FDSOI) substrates for transistors is challenging, which affects device performance characteristics such as Ion/Ioff ratio and sub-threshold voltage swing, as traditional methods struggle to reduce the channel thickness effectively.
Innovation Solution
A recessed channel structure is implemented in FDSOI transistors, where the channel region is thinned to less than 40 angstroms, with a sidewall spacer structure and gate dielectric extending conformally along the recessed surface, allowing for improved scaling of the semiconductor device layer thickness and enhanced device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional methods are used to scale semiconductor device layer thickness in FDSOI substrates, then manufacturing process simplicity is maintained, but device performance characteristics (Ion/Ioff ratio and sub-threshold voltage swing) deteriorate due to inability to reduce channel thickness effectively
Solution Approach 1:
The channel region is divided into two distinct thickness zones: a first thickness in the central channel region and a second (greater) thickness in the peripheral channel regions. This segmentation allows the central region to be thinned to less than 40 angstroms for improved device performance while the peripheral regions maintain greater thickness for structural support and manufacturability, thus resolving the contradiction between manufacturing ease and channel thickness precision.
Solution Approach 2:
Different regions of the channel are given different thickness qualities - the central region receives aggressive thinning to enhance performance characteristics, while peripheral regions retain greater thickness. This local differentiation enables precise control of device performance parameters without requiring complete thinning of the entire channel, thereby maintaining reasonable manufacturing complexity.
2Reliability
If the channel thickness is reduced to less than 40 angstroms to improve device performance, then Ion/Ioff ratio and sub-threshold voltage swing are enhanced, but manufacturing difficulty increases
Solution Approach 1:
By segmenting the channel into central and peripheral regions with different thickness requirements, the invention enables the central region to achieve the target thickness of less than 40 angstroms for superior device performance while the peripheral regions maintain greater thickness that is easier to manufacture and provides structural integrity, thus balancing reliability improvement with manufacturing feasibility.
Solution Approach 2:
The recessed channel structure is formed as a preliminary feature before final device assembly, allowing the thin central channel region to be created in advance with proper thickness control. This preliminary formation of the recessed structure enables subsequent manufacturing steps to proceed more easily, reducing overall manufacturing difficulty while achieving the required sub-40-angstrom thickness for high performance.
Data Source
AI summary
An integrated circuit includes a SOI substrate comprising a base substrate, an insulator layer, and a semiconductor device layer. Source and drain regions in the semiconductor device layer are spaced apart by a channel region in the semiconductor device layer. A gate electrode is disposed over the channel region and has a bottom surface that extends below a top surface of the semiconductor device layer. A sidewall spacer structure extends along outer sidewalls of the gate electrode and has a bottom surface that rests on the top surface of the semiconductor device layer. A gate dielectric separates the channel region from the bottom surface of the gate electrode and contacts the bottom surface of the sidewall spacer structure. The channel region beneath the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.