Recessed-Channel CMOS Thin-Film Transistor for 3D BEOL Stacking
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Solution Overview
Problem
Stacking peripheral circuits above scaled high-performance CMOS transistors poses challenges due to physical, thermal, and material incompatibilities, including size differences and higher operational voltage requirements, which existing methods struggle to address effectively.
Innovation Solution
A top gate recessed channel CMOS thin film transistor is fabricated by bonding a substrate with a blanket layer of single crystal material above prefabricated transistors, allowing for flexible fabrication without strict alignment requirements, and featuring recessed channel transistors with tunable gate length and source/drain structures to modulate effective gate length independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If peripheral circuit elements are stacked above scaled high-performance CMOS transistors, then transistor density and functionality are improved, but physical, thermal, and material incompatibilities arise
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by bonding a second substrate containing peripheral circuit elements above the first substrate with CMOS transistors. This vertical integration approach increases transistor density by utilizing the third dimension (height) rather than solely expanding in the planar direction, while maintaining electrical compatibility through careful substrate bonding and isolation structure design
Solution Approach 2:
The integrated circuit is divided into two separate substrates: a first substrate containing high-performance CMOS transistors and a second substrate containing peripheral circuit elements. These substrates are bonded together through their isolation layers, allowing each substrate to be optimized independently for its specific function while maintaining overall system compatibility and reliability
2Ease of manufacture
If substrate bonding with blanket layer of single crystal material is used, then fabrication flexibility is improved without strict alignment requirements, but manufacturing complexity increases
Solution Approach 1:
A blanket layer of single crystal material is deposited over the entire surface of the second substrate before any patterning or device fabrication steps. This preliminary action creates a uniform foundation that eliminates the need for precise alignment during subsequent processing steps, as the single crystal layer extends beyond the active device areas and provides a consistent bonding interface
Solution Approach 2:
The blanket layer of single crystal material serves as an intermediary between the substrate and the patterned device structures. This intermediate layer simplifies the bonding process by providing a uniform surface that does not require precise alignment with underlying features, while still allowing the underlying substrate to provide mechanical support and electrical isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of peripheral circuit elements with CMOS transistors without electrical failure, allowing for increased transistor density and functionality in a smaller package while maintaining compatibility and efficiency.
Implementation Method 1
bonding the first substrate with the second substrate by bringing into contact the uppermost surface of the first isolation layer with an uppermost surface of the second isolation layer
Data Source
AI summary
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.