Recessed Conductive Circuit Layer for Solder Bridging Prevention

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Solution Overview

Problem

The miniaturization of semiconductor packages leads to high bonding pad density, making it difficult to perform flip chip bonding between semiconductor chips and substrates without risking short circuits due to solder bridging between adjacent conductive traces and interconnect bumps.

Innovation Solution

A semiconductor package structure with a recessed conductive circuit layer and conductive bumps on the substrate, where the bumps are designed with a protrusion and metal layer portion to create an accommodating space for solder, preventing overflow and potential short circuits by keeping the solder material below the substrate's surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If bonding pad density is increased to miniaturize semiconductor packages, then the number of I/O connections is improved, but the risk of short circuits due to solder bridging increases

Engineering Contradiction:
Improvenumber of I/O connectionsVSAvoidrisk of short circuits
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The conductive circuit layer is recessed into the substrate along the depth dimension, creating a three-dimensional structure where the circuit layer is positioned below the top surface. This vertical displacement separates the conductive paths from the solder placement area, allowing high-density bonding pads on the surface while preventing solder bridges from contacting adjacent conductive traces, thus resolving the contradiction between increased I/O connections and reduced short circuit risk

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The substrate structure is segmented into distinct functional zones: a top surface for solder placement and bonding pads, a recessed region for conductive circuit layers, and side surfaces for mechanical support. This segmentation allows independent optimization of each zone - the top surface can accommodate high-density bonding pads while the recessed conductive layer provides electrical connectivity without exposing conductive traces to solder bridging risks

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If bonding pad density is increased, then more I/O connections are achieved, but the space around the semiconductor chip is reduced

Engineering Contradiction:
Improvebonding pad densityVSAvoidspace around semiconductor chip
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

By moving the conductive circuit layer into the depth dimension through recessing, the invention frees up surface area around the semiconductor chip. The conductive functions are maintained in the vertical dimension while the horizontal dimension becomes available for additional bonding pads, enabling higher bonding pad density without encroaching on the space around the chip

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conductive circuit layer is recessed to prevent solder bridging, then short circuit risk is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveshort circuit preventionVSAvoidsubstrate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive circuit layer is recessed into the substrate before the soldering process. This preliminary structural preparation creates built-in protection against solder bridging, eliminating the need for additional complex protective measures during assembly. The recessed structure is formed once during substrate fabrication, simplifying subsequent manufacturing steps while maintaining reliable short circuit prevention

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9978705B2Semiconductor substrate and semiconductor package structure having the same
Publication Date: 2018.05.22 ADVANCED SEMICON ENG INC
  • US9978705B2 patent drawing
  • US9978705B2 patent drawing
  • US9978705B2 patent drawing

AI summary

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.