3D Stacked Memory Cell With Recessed Conductive Layer
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is hindered by the instability of conductive paths in resistance change memory cells, leading to variations in element characteristics and interference between adjacent cells, due to challenges in forming and controlling the resistance change film and electrode structures in three-dimensional cell configurations.
Innovation Solution
A semiconductor memory device configuration where the conductive layer is recessed with respect to the insulating layer, limiting the conductive path formation region and preventing diagonal conductive paths, allowing for thinner insulating layers without mutual interference, and using specific etching and deposition methods to form a stable resistance change film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the element area is decreased to improve performance and reduce chip costs, then the charge amount capable of being accumulated decreases, but it becomes difficult to obtain a sufficient voltage difference for sensing
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional stacked structures. Multiple memory cells are stacked vertically, allowing the element area to be reduced while maintaining sufficient charge accumulation capacity. The vertical stacking enables more elements per unit area without compromising the voltage difference needed for sensing.
2Area of moving object
If conventional planar structures are used, then the area of elements is larger, but the number of mounted elements per unit area is limited
Solution Approach 1:
The patent employs vertical stacking of multiple memory cell layers to increase the density of mounted elements. By utilizing the third dimension (vertical direction), the structure achieves higher element density per unit area compared to conventional planar configurations.
Solution Approach 2:
Multiple memory cells are nested vertically in a stacked configuration, with each cell layer containing variable resistive elements, insulating layers, and conductive layers arranged in repeating patterns. This nesting approach maximizes the number of elements within a given footprint area.
3Length of moving object
If the insulating layer is made thinner to achieve further miniaturization, then the device size is reduced, but diagonal conductive paths may form between adjacent cells causing interference
Solution Approach 1:
The patent introduces asymmetric structural features, specifically retreating the conductive layer relative to the insulating layer at certain regions. This asymmetric configuration creates a stepped or offset structure that prevents diagonal conductive paths from forming through the insulating layer, even when the insulating layer is thin.
Solution Approach 2:
The retreated conductive layer acts as an intermediary structure that blocks potential diagonal conductive paths. By creating a physical discontinuity or offset in the conductive path, this intermediate structure prevents interference between adjacent cells while allowing the insulating layer to remain thin.
4Device complexity
If the conductive path formation region is not limited, then the device structure is simpler, but conductive paths become unstable and element characteristics vary
Solution Approach 1:
The patent applies local quality control by creating a specific retreated structure in certain regions where the conductive layer is offset relative to the insulating layer. This localized structural modification limits the conductive path formation region to specific areas, ensuring stable and homogeneous conductive paths while maintaining overall structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables stable and homogeneous conductive path formation, reducing mutual interference between cells and achieving miniaturization while maintaining stable element characteristics.
Implementation Method 1
when a large current is caused to flow by applying a high voltage to the metal oxide film, a microscopic path in which current flows easily in a local part, that is, a so-called filament path, is formed
Implementation Method 2
The resistance change memory is a memory that stores information by the generation or disappearance of a filament path formed in a metal oxide film
Implementation Method 3
using specific etching and deposition methods to form a stable resistance change film
Implementation Method 4
using specific etching and deposition methods to form a stable resistance change film
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of insulating layers, a plurality of first interconnection layers, a plurality of second interconnection layers, a plurality of memory cells, and a resistance change film. The insulating layers and first interconnection layers are arranged in parallel with the semiconductor substrate. The second interconnection layers are arranged so as to intersect the first interconnection layers. The second interconnection layers are arranged perpendicular to the semiconductor substrate. The memory cells are arranged at intersections of the first and second interconnection layers. Each of the memory cells includes the resistance change film arranged between the first and second interconnection layers. The side of the first interconnection layer in contact with the resistance change film is retreated more in a direction to separate from the second interconnection layer than the side of the insulating layer.