Recessed Conductive Layers in Non-Volatile Memory for Voltage Withstand
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Solution Overview
Problem
In highly integrated semiconductor memory devices, thinned interlayer dielectric films reduce the withstand voltage between memory cells, necessitating a solution to enhance integration while maintaining or improving voltage withstand in Vertical Array Line (VAL) structures.
Innovation Solution
The implementation of a memory cell array structure where the side surfaces of conductive layers are recessed from the interlayer insulating layers, allowing for the formation of continuous variable resistance layers with convex shapes on both surfaces, which enhances the withstand voltage between memory cells without increasing the thickness of interlayer dielectric films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thinned interlayer dielectric films are formed to provide more integrated memory cell array, then integration density is improved, but withstand voltage between memory cells deteriorates
Solution Approach 1:
The patent applies local quality by creating recessed regions at specific locations where word lines contact bit lines. These recessed portions are formed only in the interlayer dielectric film at the intersection areas, not throughout the entire structure. This localized modification allows the interlayer dielectric film to be thinner in non-critical areas while maintaining adequate insulation and withstand voltage at the critical contact regions between word lines and bit lines.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming recessed portions that extend downward from the surface of the interlayer dielectric film. This creates a stepped structure where the word lines make contact with bit lines at a lower level, effectively increasing the vertical separation distance between adjacent memory cells. This dimensional approach allows thinner overall interlayer dielectric films while maintaining sufficient insulation at critical interfaces.
2Volume of moving object
If smaller line width is used to make LSI devices more compact, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interlayer dielectric film structure by creating distinct recessed portions at word line-bit line contact regions. This segmentation allows different areas of the interlayer dielectric film to serve different functions: thinner regions for integration density and thicker recessed regions for electrical isolation. This segmented approach enables compact device design while maintaining manufacturing feasibility through standardized recess formation processes.
Data Source
AI summary
First conductive layers extend in a first direction horizontal to a substrate as a longitudinal direction, and are stacked in a direction perpendicular to a substrate. An interlayer insulating layer is provided between the first conductive layers. The variable resistance layers functioning as a variable resistance element are formed continuously on the side surfaces of the first conductive layers and the interlayer insulating layer. A columnar conductive layer is provided on the side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layers. First side surfaces of the first conductive layers are recessed from a second side surface of the interlayer insulating layer in the direction away from the columnar conductive layers.