Recessed Control Gate Non-Volatile Memory Eliminates Source Drain Regions
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face limitations in integration and cost due to broad source and drain regions and quality issues with single crystal layers, restricting their ability to support increased capacity and speed.
Innovation Solution
A non-volatile memory device design featuring recessed control gate electrodes, charge storage layers, and auxiliary electrodes capacitively coupled with semiconductor layers, eliminating the need for source and drain regions, and using a bulk semiconductor wafer for fabrication, which allows for higher integration and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional three-dimensional non-volatile memory devices are fabricated with broad source and drain regions, then integration is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes source and drain regions from the conventional memory device structure, replacing them with a charge storage layer coupled to the control gate. This extraction eliminates the complexity of forming and configuring broad source and drain regions while maintaining the essential memory functionality through the charge storage mechanism.
Solution Approach 2:
The patent introduces a charge storage layer as an intermediary between the control gate and the semiconductor substrate. This charge storage layer serves as a mediator that enables data storage functionality without requiring the complex source and drain region structure, thereby simplifying the overall device architecture.
2Quantity of substance
If multilayers are stacked to improve integration, then capacity increases, but manufacturing cost and quality control difficulty increase
Solution Approach 1:
The patent utilizes vertical stacking of memory cells in the third dimension to increase storage capacity. Multiple memory cells are arranged vertically above each other, allowing high capacity integration without requiring lateral expansion or complex multilayer interconnect structures that would increase manufacturing cost.
3Quantity of substance
If multilayers are stacked to improve integration, then capacity increases, but single crystal layer quality becomes harder to ensure
Solution Approach 1:
The patent divides the memory device into discrete memory cells, each with its own charge storage layer and control gate structure. This segmentation allows each cell to be independently formed with consistent quality, avoiding the propagation of defects that would occur in continuous multilayer structures. The segmented approach maintains single crystal quality while achieving high capacity through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables higher performance, increased integration, and cost-effective fabrication of non-volatile memory devices with improved memory capacity and speed, while maintaining reliability and omitting the need for source and drain regions.
Implementation Method 1
at least one first auxiliary electrode, and at least one second auxiliary electrode. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer
Data Source
AI summary
A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.