Recessed FET Source/Drain Structure for Backside Power Rail Contact
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Solution Overview
Problem
As IC devices miniaturize, the available area for forming contacts and interconnects becomes smaller, leading to increased routing complexity, parasitic resistance, and capacitance, which negatively impacts manufacturing cost and performance.
Innovation Solution
A field effect transistor (FET) structure with recessed source/drain epitaxial structures for direct backside power rail contact, featuring a gate structure between S/D epitaxial structures and a backside inter-layer dielectric layer, with the S/D structures extending below the gate and electrically coupled to backside contacts, allowing for larger contact areas and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IC devices are miniaturized to advance computing power, then computing power increases, but the available area for forming contacts and interconnects becomes smaller
Solution Approach 1:
The source/drain epitaxial structures extend vertically below the gate structure into the backside ILD layer, utilizing the third dimension (depth) to create contact area. This vertical extension allows backside contacts to be formed with larger surface area without increasing the planar footprint, effectively resolving the area constraint imposed by device miniaturization.
2Volume of moving object
If the available area for contacts and interconnects becomes smaller, then device size is reduced, but routing complexity increases
Solution Approach 1:
Instead of forming contacts from the front side of the device, the invention utilizes backside contacts where the source/drain structures extend downward through the substrate. This inversion of the contact formation approach simplifies routing by providing direct access to power rails from the backside, reducing the complexity of interconnect routing.
3Length of moving object
If the available area for contacts and interconnects becomes smaller, then device dimensions are reduced, but parasitic resistance and capacitance increase
Solution Approach 1:
By extending the source/drain epitaxial structures vertically into the backside ILD layer, the contact surface area is increased in the depth dimension. This larger contact area reduces the current density and consequently lowers parasitic resistance, while the vertical configuration also helps reduce parasitic capacitance by separating the contact region from the active device area.
Data Source
AI summary
A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure, extending in a first horizontal direction and disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure set apart in a second horizontal direction. The FET structure also comprises a backside inter-layer dielectric (ILD) layer disposed below the vertical metal gate structure and the first and second S/D EPI structures. The first S/D EPI structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure and into the backside ILD layer, the lower portion comprising sides and a bottom surface. At least the bottom surface of the lower portion is electrically coupled to a backside contact, such as a long trench contact extending in the second horizontal direction or an extended contact island.