Recessed Gate Structure for Leakage Control in Scaled Semiconductors
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while controlling leakage issues associated with smaller gate sizes.
Innovation Solution
The semiconductor device incorporates a substrate with a first peripheral region featuring recessed gates with a U-shaped cross-sectional profile and a second peripheral region with a planar gate structure. The recessed gates include a recessed gate dielectric layer, a bottom conductive layer with a valley-shaped profile, a top conductive layer, and a capping layer, allowing for simultaneous fabrication with planar gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are scaled down to increase computing ability, then device density and computing power are improved, but leakage issues and manufacturing complexity increase
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate dielectric layer, first conductive layer, second conductive layer, and capping layer. Each layer serves a specific function and can be independently optimized, allowing the device to achieve higher density while maintaining manufacturability through modular fabrication processes.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional recessed gate structures with vertical sidewalls. This dimensional change increases the effective gate area without proportionally increasing the footprint, thereby improving device density while the recessed configuration helps control leakage through better electric field confinement.
2Quantity of substance
If gate size is reduced to increase device density, then element density is improved, but leakage control becomes more difficult
Solution Approach 1:
Different regions of the gate structure have different material compositions and properties optimized for specific functions: the gate dielectric layer provides insulation, the first conductive layer provides gate control, the second conductive layer enhances capacitance, and the capping layer protects the structure. This local optimization allows effective leakage control at reduced gate dimensions.
Solution Approach 2:
The gate structure employs composite materials with different electrical and physical properties stacked in layers. The combination of dielectric materials and conductive materials creates a composite structure that simultaneously achieves high density, effective leakage control, and improved device performance through synergistic material properties.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.