Recessed-Gate MOS Transistor Fabrication via Pad Pullback
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Solution Overview
Problem
The challenge in fabricating semiconductor devices, particularly recessed-gate trench MOS transistors for DRAMs, lies in controlling the depth of recesses etched into semiconductor wafers using conventional dry etching methods, which leads to variations in threshold voltage and inconsistent device performance due to sub-micron scale dimensions.
Innovation Solution
A method involving a semiconductor substrate with a pad layer, trench capacitors, and a series of lithography and etching processes to form shallow trench isolation and self-aligned gate trenches, ensuring precise control over recess formation and gate placement, including the use of chemical mechanical polishing and selective etching to achieve uniformity across the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional dry etching methods are used to form recesses, then the fabrication process is simple, but the recess depth varies across the wafer leading to threshold voltage control problems
Solution Approach 1:
The patent introduces an intermediary material layer (such as a sacrificial layer or planarization layer) that mediates between the etching process and the final recess depth. This intermediary layer acts as a reference plane that ensures uniform recess depth across the wafer, solving the precision problem while maintaining process simplicity.
Solution Approach 2:
The patent replaces the conventional dry etching mechanical control method with a chemical or physical reference system. By using a deposited material layer with known thickness and uniformity as a etching stop reference, the system substitutes mechanical depth control with a material-based reference standard, achieving better depth uniformity.
2Area of moving object
If the feature size is reduced below 0.15 μm, then device density increases, but internal electric fields exceed the upper limit causing increased leakage and decreased retention time
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional recessed-gate or trench-type structures. By extending the gate into the substrate vertically, the effective channel length is increased without increasing the planar footprint, thereby maintaining data retention at sub-0.15 μm dimensions.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by forming recesses with specific depth-to-width ratios. This parameter change allows the effective channel length to be decoupled from the drawn channel length, enabling continued scaling while maintaining electrical performance.
3Reliability
If recess depth is increased to reduce short channel effects, then effective channel length increases, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent performs preliminary actions by depositing a reference material layer before the recess etching process. This pre-deposited layer serves as a depth reference that guides the etching process, ensuring that recesses are etched to the correct depth without requiring complex real-time depth monitoring or control during etching.
Data Source
AI summary
A method of fabricating gate trench utilizing pad pullback technology is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. The pad layer is recessed from its top and covered with a polysilicon layer. Isolation trenches are formed in the substrate and then filled with photoresist. The TTO is then stripped. The pad layer that is not covered by the photoresist is pulled back to define the gate trench.