Recessed Gate Stepped Profile Junction Shorting Prevention
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Solution Overview
Problem
Conventional recess-gate structures face issues with junction shorting due to equal junction thickness with the device isolation layer, leading to operational reliability concerns and etching challenges that result in residue and electrical connectivity between gates.
Innovation Solution
A recess-gate structure with a stepped profile gate recess, where the bottom plane is only in the active region, preventing shorting by maintaining sufficient device isolation layer thickness and allowing for accurate etching, and a method involving ion implantation to form asymmetrical junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the bottom plane of the gate recess extends over the storage node and device isolation layer to eliminate height difference, then the channel length is increased and short-channel effect is prevented, but the junction height is lowered and junction shorting occurs
Solution Approach 1:
The gate recess is segmented into two distinct planes: a top plane that contacts the gate electrode and a bottom plane that is offset from the device isolation layer. This segmentation allows the top plane to provide sufficient channel length while the bottom plane maintains adequate junction height, preventing shorting between adjacent junctions.
Solution Approach 2:
The gate recess structure transitions from a single-plane configuration to a stepped two-plane configuration. The vertical offset between the top and bottom planes creates additional spatial separation, allowing the channel to extend sufficiently while maintaining junction integrity above the offset bottom plane.
2Length of moving object
If the gate recess is etched based on the bottom plane with a predetermined slope, then the channel length is maximized, but the top plane counters a steep etching slope causing damage to adjacent junctions
Solution Approach 1:
The etching process is segmented into two distinct stages corresponding to the two planes. The first etching stage creates the bottom plane with a gentler slope that protects adjacent junctions, while the second stage forms the top plane with a steeper slope to maximize channel length. This segmented approach prevents junction damage while achieving the desired channel dimensions.
3Object-affected harmful factors
If the gate recess is etched based on the top plane with a predetermined slope, then junction damage is avoided, but the bottom plane produces a dull etching slope causing material residue that electrically connects adjacent gates
Solution Approach 1:
The etching process is divided into two sequential steps: a first etching step that forms the bottom plane with controlled slope to prevent junction damage, and a second etching step that forms the top plane with precise slope control to eliminate material residue. This segmented etching approach simultaneously achieves junction protection and high manufacturing precision.
Solution Approach 2:
The bottom plane is formed first with a protective etching slope that prevents junction damage during the initial etching phase. This preliminary action creates a foundation that protects adjacent structures before the final top plane is formed with precision etching to eliminate residue.
4Reliability
If dopant density in the channel is increased to prevent threshold voltage lowering, then short-channel effect is mitigated, but electric field concentration on source junctions increases and current leakage worsens
Solution Approach 1:
The gate recess structure creates local geometric variations that modify electric field distribution. The stepped profile with offset planes produces localized field concentration in the channel region rather than at the source junctions, allowing threshold voltage control without excessive current leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents junction shorting, enhances operational reliability by maintaining junction height, and improves resistance characteristics of bit line nodes through precise etching and ion implantation.
Implementation Method 1
a method involving ion implantation to form asymmetrical junctions
Data Source
AI summary
Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane. The bottom plane of the stepped gate recess exists in only the active region except for the device isolation region.