Selectively Recessed Reference Plane for Memory Module Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory modules face challenges in optimizing the structural design of reference planes in module tab areas, which affect signal and power integrity, leading to inefficiencies in signal transmission speed and increased inductance of power tabs.
Innovation Solution
A selectively recessed reference plane structure is implemented, where the reference plane layer is recessed below signal tabs and non-recessed below power tabs, with an insulating layer in between, to reduce parasitic capacitance and inductance, improving signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the reference plane layer is recessed below both signal tabs and power tabs, then signal transmission speed is improved, but power tab inductance increases
Solution Approach 1:
The reference plane layer is selectively recessed only below the signal tabs while remaining non-recessed below the power tabs. This local differentiation allows the structure to simultaneously reduce parasitic capacitance for signal integrity and maintain low inductance for power delivery, resolving the contradiction between signal speed and power tab inductance.
2Object-generated harmful factors
If the reference plane layer is non-recessed below power tabs, then power tab inductance is reduced, but signal transmission speed is degraded
Solution Approach 1:
The reference plane layer is selectively recessed only below the signal tabs while remaining non-recessed below the power tabs. This local differentiation allows the structure to simultaneously reduce parasitic capacitance for signal integrity and maintain low inductance for power delivery, resolving the contradiction between signal speed and power tab inductance.
3Object-generated harmful factors
If the reference plane layer is recessed below signal tabs, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The reference plane layer is segmented into different regions: recessed portions below signal tabs and non-recessed portions below power tabs. This segmentation is achieved through selective etching processes that target specific areas, allowing the complex geometry to be manufactured using standard PCB fabrication techniques without requiring entirely new manufacturing approaches.
Data Source
AI summary
A memory module includes a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area, a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab, and an insulating layer between the surface layer and the reference plane layer.