Recessed Source/Drain Strap for MUGFET Parasitic Capacitance
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Solution Overview
Problem
Conventional methods for forming electrical connections in multi-gate Field Effect Transistors (MUGFETs) introduce significant series resistance and parasitic capacitance, which hinder performance and increase power consumption due to high gate-to-source and gate-to-drain capacitances.
Innovation Solution
A recessed conductive strap is formed below the surface of the FINFETs, perpendicular to the fins, with recessed portions within the insulator layer and projected portions above, to minimize capacitance and provide a low-resistance connection between source and drain regions, while inducing physical strain in the semiconductor fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planar conductive strap is used to connect source and drain regions, then large contact area is achieved for low resistance, but capacitance between gate and strap becomes very high
Solution Approach 1:
The conductive strap is moved from a planar configuration at the surface to a recessed configuration below the surface plane of the FINFETs. This dimensional change in the vertical direction reduces the capacitance between the strap and the gate while maintaining electrical connection functionality.
Solution Approach 2:
The conductive strap is nested within the insulator layer below the fins, with recessed portions disposed within the insulator layer and projected portions extending into the fins. This nesting approach allows the strap to be embedded in the structure, reducing exposed surface area and associated capacitance.
2Ease of manufacture
If conventional fabrication methods are used, then manufacturing process is simple, but series resistance and parasitic capacitance are significant
Solution Approach 1:
The conductive strap is segmented into projected portions that extend into the fins and recessed portions that are disposed within the insulator layer. This segmentation allows the strap to maintain low resistance through large contact area while reducing capacitance by positioning portions of the strap below the surface plane.
3Productivity
If the conductive strap is positioned at the surface plane, then manufacturing is easier, but switching speed delay increases due to high gate-to-strap capacitance
Solution Approach 1:
The conductive strap is repositioned from the surface plane to a recessed position below the surface plane of the FINFETs. This vertical repositioning reduces the capacitance between the strap and gate, thereby reducing switching speed delay and improving device performance.
Data Source
AI summary
A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.