Run-Time Reconfigurable Architecture for Defect-Tolerant Logic Folding
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Solution Overview
Problem
Current reconfigurable computer architectures are limited by high defect levels in nanoelectronic circuits and lack of fine-grain temporal logic folding, restricting their application and efficiency in implementing hybrid CMOS/nanochips.
Innovation Solution
A reconfigurable computer architecture with FinFET logic elements, universal memories, and a method for temporal logic folding, enabling cycle-by-cycle reconfiguration and optimization through look-up tables, configuration RAMs, and hybrid interconnect designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If nanodevices are used to implement hybrid CMOS/nanochips, then integration density and performance are improved, but fabrication process maturity is insufficient leading to high defect levels
Solution Approach 1:
The patent implements dynamic reconfiguration capability that allows the circuit to change its structure and functionality at runtime. This enables the system to adapt to fabrication defects by rerouting signals and reconfiguring logic elements, thereby maintaining reliability despite high defect levels from immature nanofabrication processes
Solution Approach 2:
The patent changes the operational parameters of the nanodevices through voltage-controlled FinFETs and reconfiguration mechanisms. By dynamically adjusting device parameters such as conductivity and logic state, the system can compensate for manufacturing variations and defects while maintaining high integration density
2Reliability
If reconfigurable architectures are used to handle high defect levels, then reliability is improved, but fine-grain temporal logic folding capability is limited restricting application efficiency
Solution Approach 1:
The patent segments the reconfigurable architecture into fine-grain logic elements, connection switching elements, and universal memories that can be independently configured. This segmentation enables precise temporal logic folding where specific logic blocks can be folded back in time to reuse hardware resources, significantly improving application efficiency while maintaining defect tolerance
Solution Approach 2:
The patent implements dynamic temporal logic folding that allows logic elements to be reconfigured across multiple time cycles. This enables the same physical hardware to perform different logical functions at different times, achieving fine-grain resource utilization and improving application efficiency beyond static reconfiguration capabilities
3Adaptability or versatility
If universal memories are implemented to support fine-grain reconfiguration, then reconfiguration flexibility is improved, but area requirements increase
Solution Approach 1:
The patent implements universal memories that serve multiple functions: storing configuration data for logic elements, storing configuration data for connection switching elements, and supporting both fine-grain and coarse-grain reconfiguration modes. This multi-functionality reduces the total memory area required compared to having separate dedicated memories for each reconfiguration granularity level
Solution Approach 2:
The patent employs a hierarchical memory structure where configuration RAMs are distributed throughout the logic fabric in a nested arrangement. Each logic element has its configuration stored in nearby configuration RAMs, creating a nested hierarchy that minimizes area by placing memory close to the logic elements it configures, reducing both area and interconnect overhead
Data Source
AI summary
A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.