Reconfigurable BIST Testing for Sequential Memory Array Power Control
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Solution Overview
Problem
Driving multiple memory array groups from BIST engines in parallel results in high power costs and power spikes, which do not match the functional behavior of integrated circuit chips.
Innovation Solution
Implementing a reconfigurable BIST engine mode that tests memory array groups sequentially in a specified order, where the completion of one BIST engine triggers the next to begin, allowing flexibility and control over the order to avoid or reduce power spikes and high power costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple BIST engines test memory array groups in parallel, then testing speed and productivity are improved, but power consumption increases causing high power costs and power spikes
Solution Approach 1:
The patent implements a reconfigurable BIST engine mode that dynamically switches between parallel and sequential testing operations. The logic circuit responds to completion signals from BIST engines and selectively activates subsequent engines, creating a dynamic testing architecture that adapts power consumption levels based on testing progress rather than maintaining fixed parallel operation throughout
Solution Approach 2:
The patent employs periodic activation of BIST engines where engines are started sequentially based on completion signals from previous engines. This periodic action pattern allows the system to maintain high productivity when engines complete quickly while reducing power consumption during transitions, creating a rhythm of activation that balances speed and power usage
2Productivity
If multiple BIST engines test memory array groups in parallel, then testing productivity is improved, but power spikes occur that do not match functional behavior
Solution Approach 1:
The reconfigurable mode creates dynamic testing behavior that mimics real-world functional usage patterns. By transitioning from static parallel operation to dynamic sequential activation based on completion signals, the system produces power consumption profiles that more accurately reflect actual chip operational behavior during normal use
Solution Approach 2:
The patent changes the operational parameter of BIST engines from fixed parallel execution to variable sequential execution. The logic circuit modifies the activation state of subsequent engines based on completion signals, creating parameter variations in testing speed and power consumption that better match the variability seen in functional chip behavior
Data Source
AI summary
Reconfigurable testing of an integrated circuit includes storing, in a register, one or more values indicating at least a partial order in which a plurality of built-in self-test (BIST) engines are to respectively test a corresponding plurality of sets of memory arrays. A logic circuit coupled to the register causes the plurality of BIST engines to test the plurality of sets of memory arrays based on the one or more values stored in the register.