Reconfigurable Compute Fabric Loop Data I/O
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Solution Overview
Problem
Current computer architectures face limitations in performance and efficiency due to the time and energy required for data movement between processors and memory, constraining compute systems beyond the capabilities of transistor scaling.
Innovation Solution
The implementation of memory-centric compute topologies with compute-near-memory (CNM) systems, which integrate processors with memory or data storage components, utilizing hybrid threading processors and fabrics to facilitate low-latency operations through custom compute fabrics and reconfigurable compute fabrics that support synchronous flows and nested loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is moved between processors and memory using conventional architectures, then data access is possible, but time and energy consumption increase significantly
Solution Approach 1:
The patent merges memory and compute resources by integrating compute units directly within the memory device, creating a memory-compute device where processing elements are coupled to memory arrays. This integration eliminates the need for data to be moved between separate processor and memory components, thereby reducing both access time and energy consumption associated with data transfer operations.
2Productivity
If compute resources are integrated with memory, then compute efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the memory-compute device into distinct functional components including memory arrays, compute units, and interconnect structures. Each segment performs a specific function, allowing for modular design and independent optimization. This segmentation manages device complexity by organizing complex functionality into manageable, specialized units that can be independently designed and controlled.
Solution Approach 2:
The patent implements reconfigurable compute fabrics that can dynamically change their interconnect topology and data flow paths based on the computational task being performed. This dynamic reconfiguration allows the same hardware structure to adapt to different algorithms and workloads, improving compute efficiency while managing complexity through software-controlled flexibility rather than hardwired dedicated structures.
3Adaptability or versatility
If reconfigurable compute fabrics are used, then adaptability to different workloads improves, but control complexity increases
Solution Approach 1:
The patent implements a universal compute fabric architecture that can perform multiple functions through a single reconfigurable structure. The same interconnect network and compute units can be configured to execute different types of operations (e.g., neural network inference, matrix operations, data processing) by changing configuration parameters rather than requiring separate dedicated hardware for each workload type. This universality improves adaptability while controlling complexity by eliminating the need for multiple specialized subsystems.
Data Source
AI summary
Various examples are directed to systems and methods in which a first flow controller of a first synchronous flow may receive an instruction to execute a first loop using the first synchronous flow. The first flow controller may determine a first iteration index for a first iteration of the first loop. The first flow controller may send, to a first compute element of the first synchronous flow, a first synchronous message to initiate a first synchronous flow thread for executing the first iteration of the first loop. The first synchronous message may comprise the iteration index. The first compute element may execute an input/output operation at a first location of a first compute element memory indicated by the first iteration index.