Dynamically Reconfigurable Processing Core for Mixed-Mode Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current mixed-mode computing approaches face efficiency and performance limitations due to excessive data movement between different compute types, such as CPUs and GPUs, which restricts scalability and performance in handling diverse workload types like hyper-sparse graph analytics and dense AI tasks.
Innovation Solution
A dynamically reconfigurable processing core that supports multiple compute modes, including MIMD, tensor, SIMD, and scalar modes, allowing for efficient task execution without the need for costly data replication between specialized hardware units, by dynamically switching between these modes based on application requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is copied between different compute types (CPU and GPU), then task-level parallelism can be achieved, but excessive data movement occurs which limits efficiency and scalability
Solution Approach 1:
The patent combines multiple compute types (CPU, GPU, and specialized accelerators) into a single unified processing system where different processing elements can cooperate on the same data without requiring data to be copied out and moved between separate systems. This merging eliminates the data movement overhead while maintaining the benefits of task-level parallelism across heterogeneous compute units.
Solution Approach 2:
The unified processing system is designed to handle multiple workload types (sparse graph analytics, dense AI tasks, and general computing) within a single architecture that can dynamically allocate tasks to appropriate processing elements. This multi-functionality allows the system to maintain high efficiency across diverse workloads without requiring separate specialized systems for each workload type.
2Productivity
If specialized hardware units are used for different workload types, then compute efficiency is improved, but data replication between units increases which limits scalability
Solution Approach 1:
The patent merges specialized hardware units into a unified processing system where a single copy of data can be accessed by multiple processing elements simultaneously. This eliminates the need for data replication between separate specialized units while maintaining compute efficiency through targeted task allocation to appropriate processing elements within the unified system.
3Adaptability or versatility
If heterogeneous architecture is used for mixed-mode computing, then different workload types can be handled, but excessive data movement occurs which reduces performance
Solution Approach 1:
The unified processing system provides universal support for multiple workload types (sparse graph analytics, dense AI tasks, and general computing) within a single architecture. The system can dynamically adapt to different workload requirements and allocate tasks to appropriate processing elements without requiring data to be moved between separate heterogeneous systems, thereby maintaining high performance while supporting mixed-mode computing.
Data Source
AI summary
Technology described herein provides a dynamically reconfigurable processing core. The technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. In embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. In embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.