Reconfigurable Test Logic for Simultaneous DUT Block Testing
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Solution Overview
Problem
Traditional functional simulation validation environments struggle with efficiently testing multiple internal blocks of a Device Under Test (DUT) due to inflexibility in adapting to changing corner case requirements, difficulty in generating input stimuli for uncommon scenarios, and high validation costs.
Innovation Solution
A method and system utilizing a reconfigurable internal buffer and multiplexers to simultaneously test multiple DUT internal blocks by receiving input stimuli through configuration registers, selecting blocks via control registers, and enabling multiplexers to send stimuli for testing, generating outputs, and storing results for analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional functional validation environment is used to test DUT internal blocks, then testing can be performed at DUT boundary interfaces, but it becomes difficult and time-consuming to generate input stimuli for corner cases and requires higher validation cost
Solution Approach 1:
The validation environment is designed to test multiple DUT internal blocks simultaneously using a single reconfigurable test logic unit. The system can selectively enable different internal blocks through control registers, making the testbench universal and adaptable to various testing scenarios without requiring separate testbenches for each block or corner case.
Solution Approach 2:
The test logic is made reconfigurable through control registers that can dynamically select which internal blocks to test and how to route input stimuli. This dynamic configuration allows the system to adapt to changing corner case requirements and different testing scenarios without hardware changes, reducing validation costs and improving efficiency.
2Reliability
If separate test cases are created for each corner case scenario, then comprehensive coverage can be achieved, but it requires significant manual effort and time
Solution Approach 1:
Multiple corner case test scenarios are merged into a single reconfigurable test logic unit. By combining the testing capability for multiple internal blocks and corner cases into one unified system, the patent eliminates the need to create and maintain separate test cases for each scenario, significantly reducing manual effort and time while maintaining comprehensive coverage.
Solution Approach 2:
The system uses control registers to change parameters (which internal blocks are tested, how stimuli are routed) rather than creating separate test cases. By parameterizing the test configuration, the system can adapt to different corner cases through register settings rather than requiring separate test case implementations, reducing time and effort.
3Adaptability or versatility
If traditional testbench components (monitor, driver, scoreboard) are used, then functional validation can be performed, but the system lacks flexibility to quickly adapt to changing corner case requirements
Solution Approach 1:
The reconfigurable test logic unit serves multiple functions: it can test different internal blocks, generate different input stimuli patterns, and adapt to various corner case scenarios all through a single unified interface. This universality provides high adaptability while maintaining operational simplicity, as users only need to configure control registers rather than modify the entire testbench.
4Productivity
If input stimulus is driven only at DUT input interfaces, then traditional validation flow is maintained, but internal blocks cannot be tested efficiently in isolation
Solution Approach 1:
The patent segments the DUT into multiple internal blocks that can be independently selected and tested. By dividing the DUT functionality into testable segments and providing selective access through control registers, the system enables efficient isolated testing of internal blocks while maintaining a relatively simple test logic structure compared to traditional approaches.
Solution Approach 2:
The reconfigurable test logic acts as an intermediary between the traditional testbench components and the DUT internal blocks. It provides a layer of abstraction that enables efficient internal block testing by selectively routing stimuli and capturing responses, without requiring fundamental changes to the overall validation architecture.
Data Source
AI summary
A method for simultaneously testing multiple Device Under Test (DUT) internal blocks is disclosed. The method includes receiving by a reconfigurable internal buffer of a DUT, an input stimulus corresponding to at least one of a plurality of DUT internal blocks; selecting, via a control register, one or more DUT internal blocks from the plurality of DUT internal blocks to perform testing based on the input stimulus. The method to select the one or more DUT internal blocks includes enabling control bits of at least one multiplexer associated with the one or more DUT internal blocks. The method includes sending, by the reconfigurable internal buffer, the input stimulus corresponding to each of the one or more DUT internal blocks; testing the one or more DUT internal blocks based on the corresponding input stimulus; and generating, by each of the one or more DUT internal blocks, a corresponding output.