Reconfigurable Fabric for Integrated Multi-Stage Image Processing

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Solution Overview

Problem

Existing image capture devices require multiple discrete processing chips, leading to increased board space, power consumption, and limited flexibility due to the use of application-specific integrated circuits (ASICs), which are inflexible and slower than hardware-based processing.

Innovation Solution

Utilizing a reconfigurable fabric device (RFD) that can be programmed to perform multiple stages of image processing, such as ISP, DLA, encoding, BBP, and DFP, within a single integrated circuit, allowing for flexible and efficient image processing without the need for multiple chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple discrete processing chips are used for image processing, then processing functionality is comprehensive, but board space increases and device complexity increases

Engineering Contradiction:

Improveprocessing functionalityVSAvoidboard space

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple discrete processing chips (ISP, DLA, encoder, BBP, DFP) into a single integrated reconfigurable fabric device. This merging eliminates the need for multiple separate chips while maintaining all processing functionalities, directly reducing board space and device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The reconfigurable fabric device serves as a universal processing platform that can perform multiple image processing functions (ISP, DLA, encoding, BBP, DFP) through software configuration rather than requiring dedicated hardware for each function. This multi-functionality approach maintains comprehensive processing capability while using a single chip.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If ASICs are used for image processing, then processing speed is fast, but flexibility is limited

Engineering Contradiction:

Improveprocessing speedVSAvoidflexibility

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a reconfigurable fabric device that allows dynamic reconfiguration of processing pipelines through software. This enables the system to adapt processing architectures on-the-fly, providing both the speed of hardware implementation and the flexibility of software reprogramming, unlike fixed ASICs.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The reconfigurable fabric device changes its operational parameters and architecture through software configuration. Different processing stages (ISP, DLA, encoding, etc.) are implemented by reconfiguring the same hardware fabric, allowing rapid adaptation to different processing requirements while maintaining high-speed hardware execution.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If multiple discrete processing chips are used, then processing stages can be specialized, but power consumption increases

Engineering Contradiction:

Improveprocessing stage specializationVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

By merging multiple specialized processing chips into a single reconfigurable fabric device, the patent reduces the total power consumption associated with multiple independent chips, their separate power supplies, and inter-chip communication. The unified architecture allows shared resources and more efficient power management.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If software-based processing is used, then flexibility is high, but processing speed is slow

Engineering Contradiction:

ImproveflexibilityVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces software-based processing with hardware-based reconfigurable fabric processing. The same flexibility and adaptability previously requiring software interpretation is now achieved through hardware reconfiguration, providing both high-speed hardware execution and software-level flexibility through programmable logic.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250227394A1Methods and apparatus for integrated image signal processing

Publication Date: 2025.07.10 MICRON TECHNOLOGY INC

AI summary

Methods and apparatus for performing multi-step image processing using a reconfigurable fabric device (RFD) in place of multiple discrete ICs. In one embodiment, the methods and apparatus operate according to a flexible time-divided schedule, and the processing is configured to process image sensor data by at least: (i) receiving RAW image data, programming an RFD to operate as a first functional unit such as an image signal processor (ISP), using the programmed RFD to perform image signal processing on the RAW image data, storing the ISP-result in temporary memory; and (ii) programming the RFD to operate as a second functional unit (e.g., deep learning accelerator (DLA)), using the programmed RFD to read out ISP-result from the temporary memory, perform deep learning processing on the ISP-result, and storing the DLA-result back into the temporary memory. In one variant, an on-die controller and memory are used in support of the RFD operations, thereby enabling a single-die processing solution.