Reconfigurable Instruction Extensions for Post-Silicon Processor Adaptability
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Solution Overview
Problem
Existing computer processors, especially application-specific ones, are limited in functionality as their instruction sets cannot be extended post-silicon fabrication, and initiating computations in programmable logic devices like FPGAs is costly and inefficient due to overhead and lack of direct connection between the processor's data path and reconfigurable hardware.
Innovation Solution
A processing system with reconfigurable instruction extensions, comprising a processor, programmable logic, a register file, and a load/store module, allows for dynamic configuration of instruction extensions through an extension adapter, enabling the execution of new instructions post-silicon and optimizing data transfer between the register file and system memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If instructions are added using TIE language and TIE compiler before fabrication, then the processor can execute extended instructions, but the instruction set cannot be extended after fabrication and characteristics cannot be modified post-silicon
Solution Approach 1:
The patent implements dynamic reconfiguration capability in the processor, allowing the instruction set characteristics to be modified post-silicon through a reconfiguration interface. The processor can switch between different instruction set configurations during operation, transforming the static instruction set into a dynamic, adaptable system that can respond to changing computational requirements after fabrication.
2Adaptability or versatility
If reconfigurable hardware is used as a slave co-processor, then new instructions can be implemented, but computational overhead increases and execution efficiency decreases due to explicit hand control and waiting
Solution Approach 1:
The patent merges the reconfigurable hardware array with the processor's data path, creating an integrated system where the array operates as a unified computational unit rather than a separate slave co-processor. This integration eliminates the need for explicit hand control and waiting, allowing seamless execution of reconfigurable instructions within the main processor workflow.
Solution Approach 2:
The patent introduces an instruction translation mechanism that acts as an intermediary between the processor's native instruction set and the reconfigurable array's operations. This translator automatically converts high-level instructions into array-specific operations, eliminating the overhead of explicit control and synchronization while maintaining efficient execution.
3Device complexity
If reconfigurable array and processor share common path to cache and memory, then resource utilization improves, but there is no direct connection between processor's data path and array causing communication overhead
Solution Approach 1:
The patent adds a direct data path connection between the processor and reconfigurable array, creating a new communication dimension that bypasses the shared cache-memory path. This direct connection enables high-speed data transfer for array operations while maintaining the shared resource architecture for other purposes, effectively solving the communication bottleneck.
Data Source
AI summary
A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.