Reconfigurable Logic Blocks With Local Storage for Faster Processing
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Solution Overview
Problem
Reconfigurable logic circuits face challenges in efficiently utilizing hardware resources and improving processing performance without increasing clock frequency, which leads to power consumption and heat generation issues.
Innovation Solution
A reconfigurable device with multiple processing blocks, each equipped with a logic operation unit and a storage unit that can store operation results, allows for dynamic reconfiguration of logic operations based on configuration data, enabling flexible use of hardware resources and improving processing speed without raising clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency of the entire system is raised to improve processing performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The system divides the processing functionality into multiple reconfigurable logic blocks that can be independently configured and activated. Only the necessary logic blocks required for the current task are activated, allowing the system to achieve high processing performance for specific functions without raising the clock frequency of the entire system, thus avoiding excessive power consumption.
Solution Approach 2:
The patent implements dynamic reconfiguration of logic blocks based on the current processing requirements. The system can change the configuration of logic blocks during operation to optimize resource usage for different tasks, enabling efficient processing without requiring continuous high-frequency operation of all components.
2Productivity
If the clock frequency of only a unit where processing power is insufficient is raised, then processing performance of that unit is improved, but device complexity increases due to need for compensation circuits
Solution Approach 1:
The patent creates a universal reconfigurable logic block that can perform multiple different logic functions through configuration changes. This multi-functional approach eliminates the need for separate dedicated circuits for different logic operations, reducing overall device complexity while maintaining the ability to improve processing performance of specific units when needed.
Solution Approach 2:
The logic blocks can dynamically change their configuration to match the required processing function. This dynamic adaptability allows a single standardized block design to replace multiple specialized circuits, simplifying the overall device architecture while providing the flexibility to optimize processing performance for specific tasks.
3Reliability
If hardware resources are allocated for all possible functions in a conventional dedicated LSI, then reliability is improved, but hardware resource efficiency deteriorates when functions are not being used
Solution Approach 1:
The system dynamically reconfigures logic blocks based on current operational requirements. Functions that are currently needed are activated and configured, while functions that are not needed are deactivated or reconfigured for other purposes. This ensures that the system maintains reliability for active functions while maximizing hardware resource efficiency by avoiding idle allocation.
Solution Approach 2:
The patent implements a mechanism where hardware resources are temporarily allocated to specific functions when needed and then released or reconfigured for other uses when no longer required. This dynamic allocation and recovery of hardware resources ensures both reliability for active functions and high resource utilization efficiency.
Data Source
AI summary
There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing blocks. Each processing block (13) includes a logic operation unit (21) whose logic is determined by configuration data (17) and a storage unit (40) for storing processing results of the logic operation unit. Each storage unit (40) includes a plurality of storage elements (31r), input means (32) for selecting one of the plurality of storage elements (31r) based on the configuration data (17) to store the output of the logic operation unit (21), and output means (33) for connecting the plurality of storage elements (31r) to the routing matrix (15).