Reconfigurable Processor Arrays for Bulk Data Parallelism
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Solution Overview
Problem
Current processors are inefficient in processing bulk data due to limitations in instruction, data, and thread level parallelism, necessitating a reconfigurable solution that can dynamically adjust hardware configuration for optimal computation.
Innovation Solution
A reconfigurable processor with a configurable memory and multiple reconfigurable arrays that receive task execution instructions and configuration information, allowing each array to execute tasks using multiple function units, with synchronization mechanisms to ensure data acquisition and optimal resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current processors use traditional instruction level parallelism, data level parallelism, and thread level parallelism methods, then some computation performance is improved, but the overall efficiency in processing bulk data remains insufficient
Solution Approach 1:
The processor employs reconfigurable arrays that can dynamically change their hardware configuration based on the computation requirements. The configuration memory stores different configuration data that can be loaded to reconfigure the arrays for different operations, enabling the system to adapt its hardware structure dynamically rather than being fixed, thus improving bulk data processing efficiency while maintaining flexibility.
Solution Approach 2:
The processor is divided into multiple independent reconfigurable arrays, each capable of performing computations independently. This segmentation allows parallel processing of bulk data across multiple arrays, significantly improving productivity. Each array can be configured separately and operates autonomously, providing both parallelism and adaptability.
2Speed
If the number of reconfigurable arrays is increased to improve parallelism, then computation speed is improved, but device complexity and area increase
Solution Approach 1:
Multiple reconfigurable arrays are designed with identical or similar structures, each capable of performing the same range of operations. This universality means that the same configuration can be applied to all arrays, simplifying the control logic and configuration management. The arrays can be configured simultaneously using the same configuration data from the configuration memory, reducing overall device complexity while maintaining high computation speed through parallel execution.
3Power
If reconfigurable arrays are used to provide hardware-level parallelism, then computation speed is improved, but power consumption increases
Solution Approach 1:
The processor activates only the necessary number of reconfigurable arrays and function units based on the specific computation task requirements. Not all arrays need to be active simultaneously for every operation. The configuration memory enables selective activation and deactivation of arrays, allowing the system to use partial parallelism when sufficient, thereby reducing power consumption while still achieving the required computation speed for bulk data processing.
Data Source
AI summary
Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.