Reconfigurable Processor Clustering for Configuration Time
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Solution Overview
Problem
Current reconfigurable processor designs face challenges in reducing configuration time, power consumption, and hardware reuse due to inefficient task scheduling and network architectures, particularly in multimedia processing applications like MPEG-4, where computational complexity varies significantly across modes and operations.
Innovation Solution
A dynamically reconfigurable processor is designed using a methodology that identifies correlated compute-intensive regions within applications, employs a reduced complexity graph matching algorithm for pre-processing, and implements reconfiguration-aware static scheduling to manage task and resource dependencies, along with a heterogeneous hierarchical routing architecture for efficient resource allocation and interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional FPGA reconfiguration approaches are used, then hardware flexibility and programmability are improved, but configuration time and power consumption increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-organizing configuration data into hierarchical clusters before runtime. Compute-intensive regions are identified and grouped into clusters during design time, with configuration data pre-processed and stored in a hierarchical structure. This allows the reconfigurable processor to load and switch between pre-organized configuration clusters much faster than traditional approaches that configure the entire device at once.
Solution Approach 2:
The patent segments the reconfigurable processor configuration into hierarchical clusters of compute-intensive regions. Instead of treating the entire FPGA as a single reconfigurable unit, the configuration is divided into smaller, independent clusters that can be loaded and switched separately. This segmentation enables partial reconfiguration and reduces the overall configuration time and data transfer requirements.
2Adaptability or versatility
If traditional FPGA reconfiguration approaches are used, then hardware flexibility and programmability are improved, but power consumption increases due to redundant configurations
Solution Approach 1:
The patent applies preliminary action by performing graph matching and identifying common subgraphs during design time. Applications are analyzed to find correlated compute-intensive regions that can be shared across different application modes. Configuration data is pre-processed to eliminate redundancies, and a hierarchical cluster structure is established that maximizes resource reuse. This preliminary analysis significantly reduces runtime power consumption by avoiding redundant configuration operations.
Solution Approach 2:
The patent implements discarding and recovering by identifying and eliminating redundant configuration data across different application modes. The graph matching algorithm detects common subgraphs that represent shared compute-intensive regions, allowing the system to discard duplicate configuration data and recover resources for other uses. This reduces both the configuration memory requirements and the power needed for configuration operations.
3Loss of time
If compute-intensive regions are localized in specific chip areas, then configuration time is reduced and power consumption decreases, but requires sophisticated task scheduling and resource allocation
Solution Approach 1:
The patent applies preliminary action by performing comprehensive graph matching and task scheduling analysis during the design phase. The system identifies all compute-intensive regions, determines their spatial relationships, and pre-calculates optimal scheduling strategies for different application modes. This preliminary work creates a detailed map of resource dependencies and execution patterns, which greatly simplifies runtime scheduling decisions and reduces the complexity of dynamic resource allocation.
4Loss of time
If hierarchical network architecture with RAM-style configuration loading is used, then individual configuration loading time is reduced by 2-4 times, but redundant and repetitive configurations remain high
Solution Approach 1:
The patent applies preliminary action by performing graph isomorphism detection and common subgraph identification during design time. The system analyzes the application's control data flow graph to find repeated computational patterns and correlated compute-intensive regions. Configuration data is pre-processed to extract and eliminate redundancies, storing only unique configuration clusters with references to shared resources. This preliminary analysis dramatically reduces the amount of redundant configuration data that would otherwise need to be loaded repeatedly.
Solution Approach 2:
The patent implements copying by creating a hierarchical cluster structure where shared compute-intensive regions are defined once and then referenced by multiple application modes. Instead of copying the same configuration data multiple times, the system creates a single master copy of shared clusters and uses symbolic references to instantiate them across different modes. This reduces configuration memory usage and loading time while maintaining the ability to quickly switch between application variants.
Data Source
AI summary
A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed. Scheduling of the overall code is effected for sequencing, providing fastest run times and the code is implemented in hardware by partitioning and placement of processing elements on a chip and design of the connective fabric for the design elements.