Reconfigurable Processors with Rotating Buffers for Dataflow
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Solution Overview
Problem
Current semiconductor chips and systems face inefficiencies in data handling due to their reliance on control flow architectures, which are not well-suited for processing large amounts of unstructured data, leading to performance bottlenecks in applications like artificial intelligence and machine learning.
Innovation Solution
Interconnecting reconfigurable programmable processors controlled by rotating circular buffers allows for improved data handling performance by enabling processors to operate on a common instruction cycle and dynamically reconfigure operations based on data availability, enhancing dataflow processing speed and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control flow architecture is used in semiconductor chips, then existing programming models can be used, but data handling performance is inefficient for large unstructured data
Solution Approach 1:
The patent implements a dynamic dataflow architecture where the execution graph can be dynamically reconfigured based on data characteristics. The system automatically adapts the computation graph structure to match the specific data processing requirements, enabling efficient handling of large unstructured data while maintaining versatility through programmable reconfiguration.
Solution Approach 2:
The system changes fundamental parameters of data processing by transitioning from control-flow based execution to dataflow-based execution. This parameter change allows the system to process data differently - focusing on data-driven execution where operations are triggered by data availability rather than program counter progression, thereby improving performance for unstructured data.
2Adaptability or versatility
If programming logic devices are used, then adaptability to future changes is achieved, but programming time is much longer than execution time
Solution Approach 1:
The system performs preliminary compilation of dataflow graphs into optimized execution representations before actual data processing begins. This preliminary action prepares the execution plan in advance, so that when data arrives, the system can execute directly without time-consuming runtime programming or reconfiguration, thus reducing the gap between programming time and execution time.
Solution Approach 2:
The patent replaces traditional software programming mechanisms with a dataflow graph compilation system. Instead of manually writing and interpreting programming code, the system automatically compiles dataflow descriptions into efficient execution graphs, substituting the mechanical process of line-by-line program execution with a more efficient graph-based execution model that bridges the time gap between programming and execution.
3Productivity
If dataflow architecture is implemented, then data handling performance is improved, but system complexity increases
Solution Approach 1:
The system segments the dataflow execution into independent graph nodes and edges that can be processed in parallel. By dividing the computation into discrete, manageable units (operations, data types, execution contexts), the system achieves high data processing speed while keeping each individual segment simple and easier to manage, thus reducing overall system complexity through modular segmentation.
Solution Approach 2:
The patent implements a universal dataflow execution engine that can handle multiple data types and operations through a single unified architecture. This multi-functional system uses a common execution context and graph management mechanism for diverse processing tasks, thereby achieving high performance for various workloads without proportionally increasing system complexity, as the same core infrastructure serves all purposes.
Data Source
AI summary
A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.