Reconfigurable Scan Latch Cells Without Extra Hold Buffers
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Solution Overview
Problem
The integration of semiconductor chips requires efficient testing methods to maintain quality and reduce time and resource expenditure, but existing design for testability (DFT) technologies face challenges in optimizing test modes and reducing power consumption.
Innovation Solution
A standard cell library and integrated circuit (IC) design that includes a reconfigurable latch capable of switching between flip-flop and latch modes based on a scan enable signal, allowing for enhanced operation speed and reduced power consumption in function operation while omitting the need for additional hold buffers in scan test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a reconfigurable latch is used to switch between flip-flop and latch modes, then operation speed and power consumption are improved in function mode, but device complexity increases
Solution Approach 1:
The latch circuit is designed to dynamically reconfigure its operation mode between flip-flop and latch based on the scan enable signal. The circuit structure allows transient feedback paths to be enabled or disabled, changing the circuit's behavior from synchronous (flip-flop) to asynchronous (latch) operation, thereby achieving high-speed performance in function mode while maintaining testability in scan mode
Solution Approach 2:
The reconfigurable latch serves multiple functions: it operates as a flip-flop during scan testing to enable proper test signal propagation, and as a latch during normal function operation to achieve high-speed performance. This multi-functionality eliminates the need for separate hold buffers, reducing overall device complexity despite the reconfiguration capability
2Reliability
If additional hold buffers are added for scan testing, then test reliability is improved, but area and power consumption increase
Solution Approach 1:
The reconfigurable latch is designed to inherently provide the hold function required for scan testing when operated in flip-flop mode. This eliminates the need for additional dedicated hold buffers, as the same latch circuit serves both as the functional storage element and as the hold buffer during testing, thereby maintaining test reliability without increasing area
Solution Approach 2:
The functionality of the hold buffer is merged with the reconfigurable latch itself. By configuring the latch to operate in flip-flop mode during scan testing, the latch inherently provides the necessary hold function, combining multiple functions into a single circuit element and eliminating redundant components that would increase area and power consumption
3Reliability
If additional hold buffers are added for scan testing, then test reliability is improved, but power consumption increases
Solution Approach 1:
The reconfigurable latch serves as both the functional storage element and the hold buffer during scan testing. This multi-functionality eliminates the need for additional power-consuming hold buffers, as the same circuit element provides both functions at different times, thereby maintaining test reliability while minimizing power consumption
Solution Approach 2:
The hold buffer function is merged with the reconfigurable latch, eliminating redundant circuitry. During scan mode, the latch operates as a flip-flop and inherently provides the hold function, avoiding the need for separate hold buffers that would consume additional power, thus reducing overall power consumption while maintaining test reliability
Data Source
AI summary
An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.