Redistribution Circuit Structure Etching and Adhesion
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing compact integrated fan-out packages with high packing densities due to limitations in the redistribution circuit structure manufacturing process, particularly in achieving uniformity and preventing issues like broken traces and peeling in sparse areas during etching.
Innovation Solution
A method involving the formation of a redistribution circuit structure using a seed layer and barrier layer with a dry etching process to form conductive patterns, followed by plasma treatment, which ensures uniform pattern loss and enhanced adhesion, addressing the challenges of uniformity and trace integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form redistribution circuit structures, then manufacturing simplicity is maintained, but uniformity is poor and broken traces occur in sparse areas
Solution Approach 1:
The etching process is divided into multiple discrete steps: forming mandrels with specific pitch, depositing first and second sacrificial layers, selective removal of sacrificial layers, and forming second mandrels. This segmentation allows each step to be optimized independently, achieving uniform pattern transfer while avoiding the complexity of developing a single complex etching process.
Solution Approach 2:
Mandrels are formed in advance with a pitch smaller than the final conductive pattern pitch. This preliminary structuring enables subsequent steps to achieve uniform pattern formation without requiring complex real-time etching control, thereby improving manufacturing precision without proportionally increasing process complexity.
2Productivity
If feature size is reduced to increase integration density, then packing density is improved, but manufacturing precision deteriorates due to etching uniformity issues
Solution Approach 1:
Different regions of the pattern are formed using different approaches: dense regions use direct etching from first mandrels, while sparse regions use a multi-step process with sacrificial layers and second mandrels. This local quality approach ensures high manufacturing precision in both dense and sparse areas, enabling overall higher integration density without sacrificing pattern formation precision.
Solution Approach 2:
The process uses parameter changes in mandrel pitch (smaller than final pattern pitch) and material properties (different sacrificial layers with different removal characteristics) to achieve uniform pattern formation at reduced feature sizes. This allows increased integration density while maintaining manufacturing precision through controlled parameter variations.
3Adaptability or versatility
If multi-layer conductive patterns are formed to create redistribution circuit structures, then functionality is improved, but adhesion issues and peeling occur
Solution Approach 1:
Sacrificial layers serve as intermediaries between the mandrel structure and the final conductive patterns. These intermediate layers enable controlled deposition and removal processes that ensure proper adhesion of conductive layers to the substrate and to each other, preventing peeling while maintaining the required circuit functionality.
Solution Approach 2:
Material parameters are changed between different layers (different sacrificial layer materials with different removal characteristics) to optimize adhesion properties at each interface. This allows multi-layer conductive patterns to be formed with improved reliability by preventing peeling through controlled material selection and deposition parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of redistribution circuit structures with fine pitch traces, improving yield and quality by reducing the loading effect during etching and preventing issues like broken traces and peeling, thus facilitating the creation of compact and reliable integrated fan-out packages.
Implementation Method 1
A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern
Implementation Method 2
A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon
Data Source
AI summary
Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.