Redistribution Frame Layout for Compact Low-Latency Memory Packaging
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Solution Overview
Problem
Current solutions for memory bandwidth density scaling face challenges with increased package form-factor, layer count, and footprint due to electrical coupling noises and package design complexity, particularly in 2.5D and 3D integrated circuit packaging, which affect signal latency and power integrity.
Innovation Solution
The use of an opossum redistribution frame that provides localized memory I/O routing and voltage reference planes, minimizing lateral transmission paths and reducing package layer count through direct top-to-bottom vertical interconnections, while accommodating various DRAM device configurations and improving electromagnetic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If increased package layer count and trace spacing are used to mitigate electrical coupling noises, then electromagnetic noise shielding is improved, but package form-factor expands
Solution Approach 1:
The patent transitions from lateral trace routing to vertical through-silicon via interconnections, changing the dimensionality of signal transmission. This allows electromagnetic shielding without increasing lateral package footprint, as the shielding structure extends vertically through the substrate rather than requiring expanded lateral spacing.
Solution Approach 2:
The shielding structure is nested within the existing package layers, with ground planes and shield traces integrated into the substrate stack-up. The opossum frame structure nests the memory interface components within a compact footprint, allowing enhanced shielding without proportionally increasing overall package area.
2Loss of time
If DRAM packages are placed lateral to SOC die for signal latency reduction, then signal latency is improved, but package real-estate and footprint increase
Solution Approach 1:
The patent moves memory interconnections from lateral routing on the package surface to vertical through-silicon vias penetrating the substrate. This dimensional change reduces signal path length and latency while maintaining a compact package footprint, eliminating the need for lateral DRAM package placement.
Solution Approach 2:
The opossum frame structure acts as an intermediary substrate that integrates both SOC and memory interfaces vertically. This mediator enables direct top-to-bottom interconnections between processor and memory, reducing latency without requiring expanded lateral package real-estate for separate DRAM package placement.
3Loss of time
If 2.5D and 3D packaging solutions are used for computing performance scaling, then signal latency is reduced, but power loop inductance increases
Solution Approach 1:
The patent implements localized power and ground planes within the substrate, creating low-inductance power delivery networks close to the memory interface. The opossum frame structure provides localized shielding and power routing that minimizes current loop areas, reducing power loop inductance while maintaining the performance benefits of advanced packaging.
4Object-affected harmful factors
If increased package layer count is used for electromagnetic noise coupling mitigation, then noise shielding is improved, but manufacturing complexity increases
Solution Approach 1:
The through-silicon via structure serves multiple functions simultaneously: it provides signal transmission, electromagnetic shielding, and mechanical support. The opossum frame structure integrates memory interface, power delivery, and grounding functions in a unified substrate design, reducing the need for additional dedicated shielding layers and simplifying manufacturing.
Data Source
AI summary
The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.