Redistribution Layer Circuit Compensation for Chip Displacement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In chip packaging processes, chip displacement leads to inaccurate signal connections and changes in circuit resistance due to altered wire lengths, affecting the electrical quality of the chip package.
Innovation Solution
A circuit compensation method that involves measuring chip shifts, performing circuit position compensation on redistribution layers, calculating resistance differences, and adjusting circuit proportions and lengths to achieve resistance compensation, thereby ensuring stable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If circuit position compensation is performed on the redistribution layer to correct chip displacement, then connection accuracy is improved, but circuit resistance changes due to altered wire length
Solution Approach 1:
The patent applies parameter changes by adjusting circuit design parameters (width, area, length, pattern) of specific circuits in the redistribution layer to compensate for resistance changes. After position compensation causes resistance variation, the method calculates the resistance difference and modifies physical parameters of selected circuits to restore resistance to acceptable ranges, thus resolving the contradiction between connection accuracy and resistance stability.
2Measurement precision
If chip displacement is corrected through circuit position compensation, then signal connection accuracy is improved, but electrical quality deteriorates due to resistance change
Solution Approach 1:
The patent modifies physical parameters of circuits including width, area, length, and pattern to compensate for resistance changes caused by position correction. By calculating resistance differences and adjusting these parameters, the method maintains electrical quality while preserving the improved connection accuracy from position compensation.
Solution Approach 2:
The patent applies local quality by selectively adjusting parameters of specific circuits rather than uniformly modifying the entire redistribution layer. The method identifies circuits within a calculated proportion and range that need resistance compensation, and applies parameter changes only to those local areas, thus maintaining overall system performance while correcting local resistance issues.
3Manufacturing precision
If circuit layer is adjusted to compensate for pad position shift, then chip bonding accuracy is improved, but circuit resistance value changes making electrical quality unacceptable
Solution Approach 1:
The patent adjusts physical parameters (width, area, length, pattern) of circuits in the redistribution layer to compensate for resistance changes resulting from pad position compensation. This dual-compensation approach first corrects position alignment for bonding accuracy, then adjusts circuit parameters to restore resistance values to acceptable ranges, thereby resolving both positioning and electrical quality requirements.
Data Source
AI summary
A circuit compensation method applied to pattern displacement includes: disposing at least one chip on a carrier; measuring a shift of the chip, performing circuit position compensation on a predetermined pattern of a redistribution layer, and calculating a resistance difference of the pattern before and after the circuit position compensation; estimating a circuit proportion and a range of resistance variation in the pattern needed for resistance compensation after the circuit position compensation according to the resistance difference; determining a compensation position and a scheme of circuit proportion and adjusting a circuit width, area, length, pattern, or combination thereof of a circuit within the circuit proportion according to the resistance difference; outputting a picture file of the pattern after the circuit position and resistance compensation; and forming the redistribution layer according to the picture file and electrically connecting the redistribution layer to the chip. A circuit structure is also provided.