Redistribution Layer Planarization via Shear Force Electropolishing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the context of electrochemical deposition for modern integrated circuit fabrication, particularly in high-density fan-out wafer-level packaging, achieving uniformity across redistribution layers is challenging due to significant topography variations, which affect lithography depth of focus and line size consistency, especially in fine pitch and low aspect ratio features.
Innovation Solution
A two-step process involving superfilling of vias with conductive materials like copper or invar to create overgrowth bumps, followed by electropolishing or electroetching to planarize the surface, ensuring uniformity across redistribution layers, and utilizing a combination of copper, cobalt, and invar to minimize thermal expansion and cracking risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating is used to form redistribution layers with fine pitch features, then electrical conductivity is improved, but topography variation increases affecting lithography depth of focus
Solution Approach 1:
The process is divided into two distinct steps: (1) electrodeposition to form conductive features with high electrical conductivity, and (2) chemical-mechanical polishing to restore surface flatness. This segmentation allows each step to optimize for its specific function without compromising the other, resolving the contradiction between achieving high conductivity and maintaining topography uniformity
Solution Approach 2:
Chemical-mechanical polishing is performed as a preliminary action after electrodeposition to pre-establish a flat surface before subsequent lithography processes. This preliminary surface preparation ensures that the topography is uniformed prior to the next critical step, allowing the lithography to achieve proper depth of focus despite the underlying conductive structure variations
2Productivity
If via aspect ratios are reduced for finer pitch features, then feature density is improved, but electrodeposition uniformity becomes more difficult to achieve
Solution Approach 1:
The electrodeposition process parameters are optimized specifically for low aspect ratio vias, including adjusted current density, plating bath composition, and deposition time. These parameter changes enable uniform electrodeposition even in the challenging geometry of fine-pitch, low aspect ratio vias, thereby achieving high feature density while maintaining deposition uniformity
Solution Approach 2:
The process incorporates monitoring and control mechanisms to track electrodeposition uniformity across the wafer surface. Real-time feedback allows for adjustments in plating parameters during the process, ensuring that uniformity is maintained even as feature density increases and via geometries become more challenging
3Device complexity
If single material RDL layers are used, then process complexity is reduced, but thermal expansion and cracking risks increase
Solution Approach 1:
The redistribution layer structure transitions from single-material to composite material construction, combining copper (for electrical conductivity), cobalt (for magnetic properties and dimensional stability), and invar (for low thermal expansion). This composite approach distributes thermal stress across materials with complementary properties, significantly reducing cracking risk while maintaining process manageability through established multi-layer deposition techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances topographic uniformity, improves electrodeposition uniformity, and reduces the likelihood of cracking under high temperatures, leading to more consistent and reliable redistribution layers with improved electrical and mechanical performance.
Implementation Method 1
electrochemical deposition processes are used in modern integrated circuit fabrication
Implementation Method 2
The planarizing is facilitated by a liquid chemistry that is caused to exert a horizontal shear force over the conductive line and the bump
Data Source
AI summary
Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.