Redistribution Layer Structure for Low-Resistance Semiconductor Interconnects
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Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing resistance and thermal cross-talk while optimizing signal integrity and power efficiency, particularly in high-density and high-power applications, where current connections such as bond wires and through-silicon vias (TSVs) are insufficient for advanced performance demands.
Innovation Solution
The use of redistribution structures with conductive elements, including through-interlayer vias (TIVs) and insulating layers, to create efficient pathways for vertical and lateral currents, minimizing resistance and thermal mass, and optimizing signal integrity by isolating power and ground planes, thereby enhancing power delivery and reducing thermal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires and through-silicon vias (TSVs) are used for connections, then device density can be maintained, but resistance and thermal cross-talk increase, degrading signal integrity and power efficiency
Solution Approach 1:
The patent transitions from vertical connections (TSVs) and wire bonds to a planar redistribution layer architecture where conductive elements are distributed across multiple layers in the lateral dimension. This dimensional shift reduces current path length and resistance while improving signal integrity through optimized current distribution across the package substrate.
Solution Approach 2:
The patent divides the power and signal distribution function into multiple separate conductive elements and layers rather than using single monolithic TSVs or bond wires. This segmentation allows independent optimization of power delivery, signal routing, and thermal management paths, reducing cross-talk and resistive losses.
2Productivity
If higher density connections are implemented, then device miniaturization is achieved, but thermal cross-talk and resistance increase
Solution Approach 1:
The patent introduces insulating layers as intermediary materials between adjacent conductive elements in the redistribution structure. These insulating layers provide thermal isolation that reduces thermal cross-talk while allowing the conductive elements to maintain high density for device miniaturization, effectively mediating between the conflicting requirements of density and thermal management.
3Power
If traditional connection methods (bond wires, TSVs) are used, then manufacturing is simpler, but power delivery efficiency and signal integrity are insufficient for advanced applications
Solution Approach 1:
The redistribution layer structure serves multiple functions simultaneously: it provides power delivery, signal routing, thermal management, and mechanical support through its multi-layer conductive and insulating element architecture. This multi-functionality achieves superior power delivery efficiency while consolidating what would otherwise require separate systems, thereby managing overall device complexity.
4Reliability
If conductive elements are isolated for signal integrity, then power delivery is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested hierarchical structure where conductive elements are organized within defined geometric patterns and layers, with each layer nested within the overall package substrate structure. This nesting provides natural alignment references and tolerance accumulation benefits, reducing the impact of manufacturing precision variations while maintaining the isolation needed for signal integrity.
Data Source
AI summary
A semiconductor device and method of manufacture in which a first semiconductor die is disposed along a first redistribution structure, and a second redistribution structure is disposed along an opposite side of the first redistribution structure. A third redistribution structure may be disposed along an opposite surface of the semiconductor die as the first redistribution structure. Through via structures pass through at least the first redistribution structure to connect at least one of the redistribution structures to an active surface of the semiconductor die.