Redistribution Layer Packaging for Thick Chips and Dense Pillars
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Solution Overview
Problem
Conventional chip packaging methods limit the thickness of the chip due to the height of conductive pillars being restricted by the thickness of the photoresist layer, which in turn limits the distribution density of conductive pillars, thereby restricting the thickness of the chip that can be packaged.
Innovation Solution
A package structure with a redistribution layer and conductive elements, where multiple layers of conductive pillars are stacked, and a through hole in the dielectric layer allows for a thicker active chip, with bonding pads and traces formed from the same conductive layer to reduce the number of layers and improve production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the thickness of the photoresist layer is increased to facilitate heat dissipation and increase chip thickness, then the heights of conductive pillars can be increased, but the apertures of through holes become greater which limits distribution density of conductive pillars
Solution Approach 1:
The conductive pillar formation process is segmented into multiple stages: first forming through holes in the dielectric layer, then filling them with conductive material to create conductive pillars, and finally forming additional through holes in the conductive pillars to create conductive vias. This segmentation allows independent optimization of each step, enabling high distribution density while accommodating thick chips.
Solution Approach 2:
The patent transitions from a single-layer conductive pillar structure to a multi-layer structure with conductive pillars extending through the dielectric layer and conductive vias formed within them. This dimensional evolution from 2D distribution to 3D architecture enables maintaining high distribution density while supporting increased chip thickness for heat dissipation.
2Length of stationary object
If the thickness of the photoresist layer is limited, then the heights of the conductive pillars are unable to be continuously increased, thereby limiting the thickness of the chip capable of being packaged
Solution Approach 1:
The patent implements a nested structure where conductive vias are formed inside existing conductive pillars. The conductive pillars extend through the dielectric layer, and conductive vias are subsequently formed within these pillars. This nesting approach enables continuous height increase of conductive structures without proportionally increasing overall structural complexity, as the via formation process reuses the existing pillar framework.
3Productivity
If bonding pads and traces are formed from different conductive layers, then electrical connection is achieved, but the number of layers increases reducing production efficiency
Solution Approach 1:
The patent merges the bonding pad and trace into a single continuous conductive layer. The conductive layer is formed to extend from the bonding pad region through the via holes to the trace region, creating a unified conductive path. This merging eliminates the need for separate conductive layers for pads and traces, reducing total layer count while maintaining electrical connection reliability through continuous conductivity.
Data Source
AI summary
A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.