Semiconductor Package Redistribution Layer Via Design
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently integrating semiconductor chips with redistribution layers due to technical restrictions in via placement and size, which affects production yield and design complexity.
Innovation Solution
A method involving the formation of a lower redistribution layer with a stack of insulating layers and vias, allowing for the off-centered arrangement of vias and the use of a chip-last process to reduce technical restrictions and improve production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional via placement and size restrictions are applied in semiconductor package fabrication, then manufacturing process simplicity is maintained, but production yield decreases and design flexibility is limited
Solution Approach 1:
The invention divides the semiconductor package fabrication into separate processes: forming the lower redistribution layer with its insulating layers and vias, then separately forming the semiconductor chip, and finally assembling them together. This segmentation allows each component to be optimized independently, removing via placement and size restrictions that would otherwise constrain the integrated fabrication process, thereby improving production yield
Solution Approach 2:
The lower redistribution layer, including insulating layers and vias, is formed in advance before the semiconductor chip is created. This preliminary action allows the redistribution layer to be fully prepared and optimized independently, eliminating constraints on via placement and sizing that would exist if everything were fabricated simultaneously, thus enhancing production yield and design flexibility
2Adaptability or versatility
If integrated fabrication of redistribution layer and semiconductor chip is used, then process simplicity is maintained, but design flexibility and via size optimization are restricted
Solution Approach 1:
The fabrication process is segmented into distinct stages: creating the lower redistribution layer with optimized via structures, separately fabricating the semiconductor chip, and then assembling them. This segmentation enables independent optimization of each component's design parameters, including via size and placement, without being constrained by the other component's fabrication requirements, thereby enhancing design flexibility
Solution Approach 2:
The invention transitions from a planar integrated fabrication approach to a three-dimensional stacked architecture where the lower redistribution layer and semiconductor chip are formed separately and then vertically assembled. This dimensional change allows independent optimization of via structures in the redistribution layer without constraining the chip fabrication process, improving design flexibility while managing process complexity
Data Source
AI summary
A method of fabricating a semiconductor package may include forming a lower redistribution layer, forming a stack on a portion of the lower redistribution layer, and stacking a semiconductor chip on a top surface of the lower redistribution layer. The forming of the stack may include coating a photo imagable dielectric material to form a first insulating layer on the top surface of the lower redistribution layer, forming a first via to penetrate the first insulating layer, coating a photo imagable dielectric material to form a second insulating layer on a top surface of the first insulating layer, and forming a second via to penetrate the second insulating layer.